1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 5:
291 if (opc1 == 0) {
292 if (crm == 0) {
293 if (opc2 == 0) {
294 return MISCREG_DFSR;
295 } else if (opc2 == 1) {
296 return MISCREG_IFSR;
297 }

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663 return MISCREG_VBAR;
664 } else if (opc2 == 1) {
665 return MISCREG_MVBAR;
666 }
667 } else if (crm == 1) {
668 if (opc2 == 0) {
669 return MISCREG_ISR;
670 }
671 }
672 } else if (opc1 == 4) {
673 if (crm == 0 && opc2 == 0)
674 return MISCREG_HVBAR;
675 }
676 break;
677 case 13:
678 if (opc1 == 0) {
679 if (crm == 0) {
680 switch (opc2) {
681 case 0:
682 return MISCREG_FCSEIDR;

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1761 case 2:
1762 switch (op2) {
1763 case 0:
1764 return MISCREG_SPSEL;
1765 case 2:
1766 return MISCREG_CURRENTEL;
1767 }
1768 break;
1769 }
1770 break;
1771 case 3:
1772 switch (crm) {
1773 case 2:
1774 switch (op2) {
1775 case 0:
1776 return MISCREG_NZCV;

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2140 case 1:
2141 switch (op2) {
2142 case 0:
2143 return MISCREG_ISR_EL1;
2144 case 1:
2145 return MISCREG_DISR_EL1;
2146 }
2147 break;
2148 }
2149 break;
2150 case 4:
2151 switch (crm) {
2152 case 0:
2153 switch (op2) {
2154 case 0:
2155 return MISCREG_VBAR_EL2;
2156 case 1:
2157 return MISCREG_RVBAR_EL2;
2158 }
2159 break;
2160 case 1:
2161 switch (op2) {
2162 case 1:
2163 return MISCREG_VDISR_EL2;
2164 }
2165 break;
2166 }
2167 break;
2168 case 6:
2169 switch (crm) {
2170 case 0:
2171 switch (op2) {
2172 case 0:
2173 return MISCREG_VBAR_EL3;
2174 case 1:
2175 return MISCREG_RVBAR_EL3;
2176 case 2:
2177 return MISCREG_RMR_EL3;
2178 }
2179 break;
2180 }
2181 break;
2182 }
2183 break;
2184 case 13:
2185 switch (op1) {
2186 case 0:
2187 switch (crm) {

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4089 InitReg(MISCREG_L2MERRSR_EL1)
4090 .unimplemented()
4091 .warnNotFail()
4092 .allPrivileges().exceptUserMode();
4093 InitReg(MISCREG_CBAR_EL1)
4094 .allPrivileges().exceptUserMode().writes(0);
4095 InitReg(MISCREG_CONTEXTIDR_EL2)
4096 .mon().hyp();
4097 InitReg(MISCREG_CNTHV_CTL_EL2)
4098 .mon().hyp();
4099 InitReg(MISCREG_CNTHV_CVAL_EL2)
4100 .mon().hyp();
4101 InitReg(MISCREG_CNTHV_TVAL_EL2)
4102 .mon().hyp();
4103
4104 // Dummy registers

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