1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/miscregs.hh"
41#include "base/misc.hh"
42
43namespace ArmISA
44{
45
46MiscRegIndex
47decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
48{
49 switch (crn) {
50 case 0:
51 switch (opc1) {
52 case 0:
53 switch (crm) {
54 case 0:
55 switch (opc2) {
56 case 1:
57 return MISCREG_CTR;
58 case 2:
59 return MISCREG_TCMTR;
60 case 3:
61 return MISCREG_TLBTR;
62 case 5:
63 return MISCREG_MPIDR;
64 default:
65 return MISCREG_MIDR;
66 }
67 break;
68 case 1:
69 switch (opc2) {
70 case 0:
71 return MISCREG_ID_PFR0;
72 case 1:
73 return MISCREG_ID_PFR1;
74 case 2:
75 return MISCREG_ID_DFR0;
76 case 3:
77 return MISCREG_ID_AFR0;
78 case 4:
79 return MISCREG_ID_MMFR0;
80 case 5:
81 return MISCREG_ID_MMFR1;
82 case 6:
83 return MISCREG_ID_MMFR2;
84 case 7:
85 return MISCREG_ID_MMFR3;
86 }
87 break;
88 case 2:
89 switch (opc2) {
90 case 0:
91 return MISCREG_ID_ISAR0;
92 case 1:
93 return MISCREG_ID_ISAR1;
94 case 2:
95 return MISCREG_ID_ISAR2;
96 case 3:
97 return MISCREG_ID_ISAR3;
98 case 4:
99 return MISCREG_ID_ISAR4;
100 case 5:
101 return MISCREG_ID_ISAR5;
102 case 6:
103 case 7:
104 return MISCREG_RAZ; // read as zero
105 }
106 break;
107 default:
108 return MISCREG_RAZ; // read as zero
109 }
110 break;
111 case 1:
112 if (crm == 0) {
113 switch (opc2) {
114 case 0:
115 return MISCREG_CCSIDR;
116 case 1:
117 return MISCREG_CLIDR;
118 case 7:
119 return MISCREG_AIDR;
120 }
121 }
122 break;
123 case 2:
124 if (crm == 0 && opc2 == 0) {
125 return MISCREG_CSSELR;
126 }
127 break;
128 }
129 break;
130 case 1:
131 if (opc1 == 0) {
132 if (crm == 0) {
133 switch (opc2) {
134 case 0:
135 return MISCREG_SCTLR;
136 case 1:
137 return MISCREG_ACTLR;
138 case 0x2:
139 return MISCREG_CPACR;
140 }
141 } else if (crm == 1) {
142 switch (opc2) {
143 case 0:
144 return MISCREG_SCR;
145 case 1:
146 return MISCREG_SDER;
147 case 2:
148 return MISCREG_NSACR;
149 }
150 }
151 }
152 break;
153 case 2:
154 if (opc2 == 0 && crm == 0) {
155 switch (opc2) {
156 case 0:
157 return MISCREG_TTBR0;
158 case 1:
159 return MISCREG_TTBR1;
160 case 2:
161 return MISCREG_TTBCR;
162 }
163 }
164 break;
165 case 3:
166 if (opc1 == 0 && crm == 0 && opc2 == 0) {
167 return MISCREG_DACR;
168 }
169 break;
170 case 5:
171 if (opc1 == 0) {
172 if (crm == 0) {
173 if (opc2 == 0) {
174 return MISCREG_DFSR;
175 } else if (opc2 == 1) {
176 return MISCREG_IFSR;
177 }
178 } else if (crm == 1) {
179 if (opc2 == 0) {
180 return MISCREG_ADFSR;
181 } else if (opc2 == 1) {
182 return MISCREG_AIFSR;
183 }
184 }
185 }
186 break;
187 case 6:
188 if (opc1 == 0 && crm == 0) {
189 switch (opc2) {
190 case 0:
191 return MISCREG_DFAR;
192 case 2:
193 return MISCREG_IFAR;
194 }
195 }
196 break;
197 case 7:
198 if (opc1 == 0) {
199 switch (crm) {
200 case 0:
201 if (opc2 == 4) {
202 return MISCREG_NOP;
203 }
204 break;
205 case 1:
206 switch (opc2) {
207 case 0:
208 return MISCREG_ICIALLUIS;
209 case 6:
210 return MISCREG_BPIALLIS;
211 }
212 break;
213 case 4:
214 if (opc2 == 0) {
215 return MISCREG_PAR;
216 }
217 break;
218 case 5:
219 switch (opc2) {
220 case 0:
221 return MISCREG_ICIALLU;
222 case 1:
223 return MISCREG_ICIMVAU;
224 case 4:
225 return MISCREG_CP15ISB;
226 case 6:
227 return MISCREG_BPIALL;
228 case 7:
229 return MISCREG_BPIMVA;
230 }
231 break;
232 case 6:
233 if (opc2 == 1) {
234 return MISCREG_DCIMVAC;
235 } else if (opc2 == 2) {
236 return MISCREG_DCISW;
237 }
238 break;
239 case 8:
240 switch (opc2) {
241 case 0:
242 return MISCREG_V2PCWPR;
243 case 1:
244 return MISCREG_V2PCWPW;
245 case 2:
246 return MISCREG_V2PCWUR;
247 case 3:
248 return MISCREG_V2PCWUW;
249 case 4:
250 return MISCREG_V2POWPR;
251 case 5:
252 return MISCREG_V2POWPW;
253 case 6:
254 return MISCREG_V2POWUR;
255 case 7:
256 return MISCREG_V2POWUW;
257 }
258 break;
259 case 10:
260 switch (opc2) {
261 case 1:
262 return MISCREG_DCCMVAC;
263 case 2:
264 return MISCREG_MCCSW;
265 case 4:
266 return MISCREG_CP15DSB;
267 case 5:
268 return MISCREG_CP15DMB;
269 }
270 break;
271 case 11:
272 if (opc2 == 1) {
273 return MISCREG_DCCMVAU;
274 }
275 break;
276 case 13:
277 if (opc2 == 1) {
278 return MISCREG_NOP;
279 }
280 break;
281 case 14:
282 if (opc2 == 1) {
283 return MISCREG_DCCIMVAC;
284 } else if (opc2 == 2) {
285 return MISCREG_DCCISW;
286 }
287 break;
288 }
289 }
290 break;
291 case 8:
292 if (opc1 == 0) {
293 switch (crm) {
294 case 3:
295 switch (opc2) {
296 case 0:
297 return MISCREG_TLBIALLIS;
298 case 1:
299 return MISCREG_TLBIMVAIS;
300 case 2:
301 return MISCREG_TLBIASIDIS;
302 case 3:
303 return MISCREG_TLBIMVAAIS;
304 }
305 break;
306 case 5:
307 switch (opc2) {
308 case 0:
309 return MISCREG_ITLBIALL;
310 case 1:
311 return MISCREG_ITLBIMVA;
312 case 2:
313 return MISCREG_ITLBIASID;
314 }
315 break;
316 case 6:
317 switch (opc2) {
318 case 0:
319 return MISCREG_DTLBIALL;
320 case 1:
321 return MISCREG_DTLBIMVA;
322 case 2:
323 return MISCREG_DTLBIASID;
324 }
325 break;
326 case 7:
327 switch (opc2) {
328 case 0:
329 return MISCREG_TLBIALL;
330 case 1:
331 return MISCREG_TLBIMVA;
332 case 2:
333 return MISCREG_TLBIASID;
334 case 3:
335 return MISCREG_TLBIMVAA;
336 }
337 break;
338 }
339 }
340 break;
341 case 9:
342 if (opc1 >= 0 && opc1 <= 7) {
343 switch (crm) {
344 case 0:
345 case 1:
346 case 2:
347 case 5:
348 case 6:
349 case 7:
350 case 8:
351 //Reserved for Branch Predictor, Cache and TCM operations
352 case 12:
353 case 13:
354 case 14:
355 case 15:
356 // Reserved for Performance monitors
357 break;
358 }
359 }
360 break;
361 case 10:
362 if (opc1 == 0) {
363 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
364 if (crm == 2) { // TEX Remap Registers
365 if (opc2 == 0) {
366 return MISCREG_PRRR;
367 } else if (opc2 == 1) {
368 return MISCREG_NMRR;
369 }
370 }
371 }
372 break;
373 case 11:
374 if (opc1 >= 0 && opc1 <=7) {
375 switch (crm) {
376 case 0:
377 case 1:
378 case 2:
379 case 3:
380 case 4:
381 case 5:
382 case 6:
383 case 7:
384 case 8:
385 case 15:
386 // Reserved for DMA operations for TCM access
387 break;
388 }
389 }
390 break;
391 case 12:
392 if (opc1 == 0) {
393 if (crm == 0) {
394 if (opc2 == 0) {
395 return MISCREG_VBAR;
396 } else if (opc2 == 1) {
397 return MISCREG_MVBAR;
398 }
399 } else if (crm == 1) {
400 if (opc2 == 0) {
401 return MISCREG_ISR;
402 }
403 }
404 }
405 break;
406 case 13:
407 if (opc1 == 0) {
408 if (crm == 0) {
409 switch (crm) {
410 case 0:
411 return MISCREG_FCEIDR;
412 case 1:
413 return MISCREG_CONTEXTIDR;
414 case 2:
415 return MISCREG_TPIDRURW;
416 case 3:
417 return MISCREG_TPIDRURO;
418 case 4:
419 return MISCREG_TPIDRPRW;
420 }
421 }
422 }
423 break;
424 case 15:
425 // Implementation defined
426 break;
427 }
428 warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n",
429 crn, opc1, crm, opc2);
430 // Unrecognized register
431 return NUM_MISCREGS;
432}
433
434};