1/*
2 * Copyright (c) 2010-2013, 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include "arch/arm/isa.hh"
45#include "base/misc.hh"
46#include "cpu/thread_context.hh"
47#include "sim/full_system.hh"
48
49namespace ArmISA
50{
51
52MiscRegIndex
53decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
54{
55 switch(crn) {
56 case 0:
57 switch (opc1) {
58 case 0:
59 switch (opc2) {
60 case 0:
61 switch (crm) {
62 case 0:
63 return MISCREG_DBGDIDR;
64 case 1:
65 return MISCREG_DBGDSCRint;
66 }
67 break;
68 }
69 break;
70 case 7:
71 switch (opc2) {
72 case 0:
73 switch (crm) {
74 case 0:
75 return MISCREG_JIDR;
76 }
77 break;
78 }
79 break;
80 }
81 break;
82 case 1:
83 switch (opc1) {
84 case 6:
85 switch (crm) {
86 case 0:
87 switch (opc2) {
88 case 0:
89 return MISCREG_TEEHBR;
90 }
91 break;
92 }
93 break;
94 case 7:
95 switch (crm) {
96 case 0:
97 switch (opc2) {
98 case 0:
99 return MISCREG_JOSCR;
100 }
101 break;
102 }
103 break;
104 }
105 break;
106 case 2:
107 switch (opc1) {
108 case 7:
109 switch (crm) {
110 case 0:
111 switch (opc2) {
112 case 0:
113 return MISCREG_JMCR;
114 }
115 break;
116 }
117 break;
118 }
119 break;
120 }
121 // If we get here then it must be a register that we haven't implemented
122 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
123 crn, opc1, crm, opc2);
124 return MISCREG_CP14_UNIMPL;
125}
126
127using namespace std;
128
129bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
130 // MISCREG_CPSR
131 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
132 // MISCREG_SPSR
133 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
134 // MISCREG_SPSR_FIQ
135 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
136 // MISCREG_SPSR_IRQ
137 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
138 // MISCREG_SPSR_SVC
139 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
140 // MISCREG_SPSR_MON
141 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
142 // MISCREG_SPSR_ABT
143 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
144 // MISCREG_SPSR_HYP
145 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
146 // MISCREG_SPSR_UND
147 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
148 // MISCREG_ELR_HYP
149 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
150 // MISCREG_FPSID
151 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
152 // MISCREG_FPSCR
153 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
154 // MISCREG_MVFR1
155 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
156 // MISCREG_MVFR0
157 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
158 // MISCREG_FPEXC
159 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
160
161 // Helper registers
162 // MISCREG_CPSR_MODE
163 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
164 // MISCREG_CPSR_Q
165 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
166 // MISCREG_FPSCR_Q
167 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
168 // MISCREG_FPSCR_EXC
169 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
170 // MISCREG_LOCKADDR
171 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
172 // MISCREG_LOCKFLAG
173 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
174 // MISCREG_PRRR_MAIR0
175 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
176 // MISCREG_PRRR_MAIR0_NS
177 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
178 // MISCREG_PRRR_MAIR0_S
179 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
180 // MISCREG_NMRR_MAIR1
181 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
182 // MISCREG_NMRR_MAIR1_NS
183 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
184 // MISCREG_NMRR_MAIR1_S
185 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
186 // MISCREG_PMXEVTYPER_PMCCFILTR
187 bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")),
188 // MISCREG_SCTLR_RST
189 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
190 // MISCREG_SEV_MAILBOX
191 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
192
193 // AArch32 CP14 registers
194 // MISCREG_DBGDIDR
195 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
196 // MISCREG_DBGDSCRint
197 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
198 // MISCREG_DBGDCCINT
199 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
200 // MISCREG_DBGDTRTXint
201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
202 // MISCREG_DBGDTRRXint
203 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
204 // MISCREG_DBGWFAR
205 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
206 // MISCREG_DBGVCR
207 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
208 // MISCREG_DBGDTRRXext
209 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
210 // MISCREG_DBGDSCRext
211 bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")),
212 // MISCREG_DBGDTRTXext
213 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
214 // MISCREG_DBGOSECCR
215 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
216 // MISCREG_DBGBVR0
217 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
218 // MISCREG_DBGBVR1
219 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
220 // MISCREG_DBGBVR2
221 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
222 // MISCREG_DBGBVR3
223 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
224 // MISCREG_DBGBVR4
225 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
226 // MISCREG_DBGBVR5
227 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
228 // MISCREG_DBGBCR0
229 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
230 // MISCREG_DBGBCR1
231 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
232 // MISCREG_DBGBCR2
233 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
234 // MISCREG_DBGBCR3
235 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
236 // MISCREG_DBGBCR4
237 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
238 // MISCREG_DBGBCR5
239 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
240 // MISCREG_DBGWVR0
241 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
242 // MISCREG_DBGWVR1
243 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
244 // MISCREG_DBGWVR2
245 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
246 // MISCREG_DBGWVR3
247 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
248 // MISCREG_DBGWCR0
249 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
250 // MISCREG_DBGWCR1
251 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
252 // MISCREG_DBGWCR2
253 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
254 // MISCREG_DBGWCR3
255 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
256 // MISCREG_DBGDRAR
257 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
258 // MISCREG_DBGBXVR4
259 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
260 // MISCREG_DBGBXVR5
261 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
262 // MISCREG_DBGOSLAR
263 bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")),
264 // MISCREG_DBGOSLSR
265 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
266 // MISCREG_DBGOSDLR
267 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
268 // MISCREG_DBGPRCR
269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
270 // MISCREG_DBGDSAR
271 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
272 // MISCREG_DBGCLAIMSET
273 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
274 // MISCREG_DBGCLAIMCLR
275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
276 // MISCREG_DBGAUTHSTATUS
277 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
278 // MISCREG_DBGDEVID2
279 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
280 // MISCREG_DBGDEVID1
281 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
282 // MISCREG_DBGDEVID0
283 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
284 // MISCREG_TEECR
285 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
286 // MISCREG_JIDR
287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
288 // MISCREG_TEEHBR
289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
290 // MISCREG_JOSCR
291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
292 // MISCREG_JMCR
293 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
294
295 // AArch32 CP15 registers
296 // MISCREG_MIDR
297 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
298 // MISCREG_CTR
299 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
300 // MISCREG_TCMTR
301 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
302 // MISCREG_TLBTR
303 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
304 // MISCREG_MPIDR
305 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
306 // MISCREG_REVIDR
307 bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")),
308 // MISCREG_ID_PFR0
309 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
310 // MISCREG_ID_PFR1
311 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
312 // MISCREG_ID_DFR0
313 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
314 // MISCREG_ID_AFR0
315 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
316 // MISCREG_ID_MMFR0
317 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
318 // MISCREG_ID_MMFR1
319 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
320 // MISCREG_ID_MMFR2
321 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
322 // MISCREG_ID_MMFR3
323 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
324 // MISCREG_ID_ISAR0
325 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
326 // MISCREG_ID_ISAR1
327 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
328 // MISCREG_ID_ISAR2
329 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
330 // MISCREG_ID_ISAR3
331 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
332 // MISCREG_ID_ISAR4
333 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
334 // MISCREG_ID_ISAR5
335 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
336 // MISCREG_CCSIDR
337 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
338 // MISCREG_CLIDR
339 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
340 // MISCREG_AIDR
341 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
342 // MISCREG_CSSELR
343 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
344 // MISCREG_CSSELR_NS
345 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
346 // MISCREG_CSSELR_S
347 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
348 // MISCREG_VPIDR
349 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
350 // MISCREG_VMPIDR
351 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
352 // MISCREG_SCTLR
353 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
354 // MISCREG_SCTLR_NS
355 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
356 // MISCREG_SCTLR_S
357 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
358 // MISCREG_ACTLR
359 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
360 // MISCREG_ACTLR_NS
361 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
362 // MISCREG_ACTLR_S
363 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
364 // MISCREG_CPACR
365 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
366 // MISCREG_SCR
367 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
368 // MISCREG_SDER
369 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
370 // MISCREG_NSACR
371 bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")),
372 // MISCREG_HSCTLR
373 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
374 // MISCREG_HACTLR
375 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
376 // MISCREG_HCR
377 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
378 // MISCREG_HDCR
379 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
380 // MISCREG_HCPTR
381 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
382 // MISCREG_HSTR
383 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
384 // MISCREG_HACR
385 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
386 // MISCREG_TTBR0
387 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
388 // MISCREG_TTBR0_NS
389 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
390 // MISCREG_TTBR0_S
391 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
392 // MISCREG_TTBR1
393 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
394 // MISCREG_TTBR1_NS
395 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
396 // MISCREG_TTBR1_S
397 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
398 // MISCREG_TTBCR
399 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
400 // MISCREG_TTBCR_NS
401 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
402 // MISCREG_TTBCR_S
403 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
404 // MISCREG_HTCR
405 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
406 // MISCREG_VTCR
407 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
408 // MISCREG_DACR
409 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
410 // MISCREG_DACR_NS
411 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
412 // MISCREG_DACR_S
413 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
414 // MISCREG_DFSR
415 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
416 // MISCREG_DFSR_NS
417 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
418 // MISCREG_DFSR_S
419 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
420 // MISCREG_IFSR
421 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
422 // MISCREG_IFSR_NS
423 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
424 // MISCREG_IFSR_S
425 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
426 // MISCREG_ADFSR
427 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
428 // MISCREG_ADFSR_NS
429 bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
430 // MISCREG_ADFSR_S
431 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
432 // MISCREG_AIFSR
433 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
434 // MISCREG_AIFSR_NS
435 bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
436 // MISCREG_AIFSR_S
437 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
438 // MISCREG_HADFSR
439 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
440 // MISCREG_HAIFSR
441 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
442 // MISCREG_HSR
443 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
444 // MISCREG_DFAR
445 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
446 // MISCREG_DFAR_NS
447 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
448 // MISCREG_DFAR_S
449 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
450 // MISCREG_IFAR
451 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
452 // MISCREG_IFAR_NS
453 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
454 // MISCREG_IFAR_S
455 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
456 // MISCREG_HDFAR
457 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
458 // MISCREG_HIFAR
459 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
460 // MISCREG_HPFAR
461 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
462 // MISCREG_ICIALLUIS
463 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
464 // MISCREG_BPIALLIS
465 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
466 // MISCREG_PAR
467 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
468 // MISCREG_PAR_NS
469 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
470 // MISCREG_PAR_S
471 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
472 // MISCREG_ICIALLU
473 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
474 // MISCREG_ICIMVAU
475 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
476 // MISCREG_CP15ISB
477 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
478 // MISCREG_BPIALL
479 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
480 // MISCREG_BPIMVA
481 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
482 // MISCREG_DCIMVAC
483 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
484 // MISCREG_DCISW
485 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
486 // MISCREG_ATS1CPR
487 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
488 // MISCREG_ATS1CPW
489 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
490 // MISCREG_ATS1CUR
491 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
492 // MISCREG_ATS1CUW
493 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
494 // MISCREG_ATS12NSOPR
495 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
496 // MISCREG_ATS12NSOPW
497 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
498 // MISCREG_ATS12NSOUR
499 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
500 // MISCREG_ATS12NSOUW
501 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
502 // MISCREG_DCCMVAC
503 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
504 // MISCREG_DCCSW
505 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
506 // MISCREG_CP15DSB
507 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
508 // MISCREG_CP15DMB
509 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
510 // MISCREG_DCCMVAU
511 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
512 // MISCREG_DCCIMVAC
513 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
514 // MISCREG_DCCISW
515 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
516 // MISCREG_ATS1HR
517 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
518 // MISCREG_ATS1HW
519 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
520 // MISCREG_TLBIALLIS
521 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
522 // MISCREG_TLBIMVAIS
523 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
524 // MISCREG_TLBIASIDIS
525 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
526 // MISCREG_TLBIMVAAIS
527 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
528 // MISCREG_TLBIMVALIS
529 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
530 // MISCREG_TLBIMVAALIS
531 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
532 // MISCREG_ITLBIALL
533 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
534 // MISCREG_ITLBIMVA
535 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
536 // MISCREG_ITLBIASID
537 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
538 // MISCREG_DTLBIALL
539 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
540 // MISCREG_DTLBIMVA
541 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
542 // MISCREG_DTLBIASID
543 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
544 // MISCREG_TLBIALL
545 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
546 // MISCREG_TLBIMVA
547 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
548 // MISCREG_TLBIASID
549 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
550 // MISCREG_TLBIMVAA
551 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
552 // MISCREG_TLBIMVAL
553 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
554 // MISCREG_TLBIMVAAL
555 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
556 // MISCREG_TLBIIPAS2IS
557 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
558 // MISCREG_TLBIIPAS2LIS
559 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
560 // MISCREG_TLBIALLHIS
561 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
562 // MISCREG_TLBIMVAHIS
563 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
564 // MISCREG_TLBIALLNSNHIS
565 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
566 // MISCREG_TLBIMVALHIS
567 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
568 // MISCREG_TLBIIPAS2
569 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
570 // MISCREG_TLBIIPAS2L
571 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
572 // MISCREG_TLBIALLH
573 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
574 // MISCREG_TLBIMVAH
575 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
576 // MISCREG_TLBIALLNSNH
577 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
578 // MISCREG_TLBIMVALH
579 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
580 // MISCREG_PMCR
581 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
582 // MISCREG_PMCNTENSET
583 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
584 // MISCREG_PMCNTENCLR
585 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
586 // MISCREG_PMOVSR
587 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
588 // MISCREG_PMSWINC
589 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
590 // MISCREG_PMSELR
591 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
592 // MISCREG_PMCEID0
593 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
594 // MISCREG_PMCEID1
595 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
596 // MISCREG_PMCCNTR
597 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
598 // MISCREG_PMXEVTYPER
599 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
600 // MISCREG_PMCCFILTR
601 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
602 // MISCREG_PMXEVCNTR
603 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
604 // MISCREG_PMUSERENR
605 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
606 // MISCREG_PMINTENSET
607 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
608 // MISCREG_PMINTENCLR
609 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
610 // MISCREG_PMOVSSET
611 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
612 // MISCREG_L2CTLR
613 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
614 // MISCREG_L2ECTLR
615 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
616 // MISCREG_PRRR
617 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
618 // MISCREG_PRRR_NS
619 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
620 // MISCREG_PRRR_S
621 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
622 // MISCREG_MAIR0
623 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
624 // MISCREG_MAIR0_NS
625 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
626 // MISCREG_MAIR0_S
627 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
628 // MISCREG_NMRR
629 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
630 // MISCREG_NMRR_NS
631 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
632 // MISCREG_NMRR_S
633 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
634 // MISCREG_MAIR1
635 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
636 // MISCREG_MAIR1_NS
637 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
638 // MISCREG_MAIR1_S
639 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
640 // MISCREG_AMAIR0
641 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
642 // MISCREG_AMAIR0_NS
643 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
644 // MISCREG_AMAIR0_S
645 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
646 // MISCREG_AMAIR1
647 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
648 // MISCREG_AMAIR1_NS
649 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
650 // MISCREG_AMAIR1_S
651 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
652 // MISCREG_HMAIR0
653 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
654 // MISCREG_HMAIR1
655 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
656 // MISCREG_HAMAIR0
657 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
658 // MISCREG_HAMAIR1
659 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
660 // MISCREG_VBAR
661 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
662 // MISCREG_VBAR_NS
663 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
664 // MISCREG_VBAR_S
665 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
666 // MISCREG_MVBAR
667 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
668 // MISCREG_RMR
669 bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")),
670 // MISCREG_ISR
671 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
672 // MISCREG_HVBAR
673 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
674 // MISCREG_FCSEIDR
675 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
676 // MISCREG_CONTEXTIDR
677 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
678 // MISCREG_CONTEXTIDR_NS
679 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
680 // MISCREG_CONTEXTIDR_S
681 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
682 // MISCREG_TPIDRURW
683 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
684 // MISCREG_TPIDRURW_NS
685 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
686 // MISCREG_TPIDRURW_S
687 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
688 // MISCREG_TPIDRURO
689 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
690 // MISCREG_TPIDRURO_NS
691 bitset<NUM_MISCREG_INFOS>(string("11001100110101100001")),
692 // MISCREG_TPIDRURO_S
693 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
694 // MISCREG_TPIDRPRW
695 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
696 // MISCREG_TPIDRPRW_NS
697 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
698 // MISCREG_TPIDRPRW_S
699 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
700 // MISCREG_HTPIDR
701 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
702 // MISCREG_CNTFRQ
703 bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")),
704 // MISCREG_CNTKCTL
705 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
706 // MISCREG_CNTP_TVAL
707 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
708 // MISCREG_CNTP_TVAL_NS
709 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
710 // MISCREG_CNTP_TVAL_S
711 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
712 // MISCREG_CNTP_CTL
713 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
714 // MISCREG_CNTP_CTL_NS
715 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
716 // MISCREG_CNTP_CTL_S
717 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
718 // MISCREG_CNTV_TVAL
719 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
720 // MISCREG_CNTV_CTL
721 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
722 // MISCREG_CNTHCTL
723 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
724 // MISCREG_CNTHP_TVAL
725 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
726 // MISCREG_CNTHP_CTL
727 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
728 // MISCREG_IL1DATA0
729 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
730 // MISCREG_IL1DATA1
731 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
732 // MISCREG_IL1DATA2
733 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
734 // MISCREG_IL1DATA3
735 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
736 // MISCREG_DL1DATA0
737 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
738 // MISCREG_DL1DATA1
739 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
740 // MISCREG_DL1DATA2
741 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
742 // MISCREG_DL1DATA3
743 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
744 // MISCREG_DL1DATA4
745 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
746 // MISCREG_RAMINDEX
747 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
748 // MISCREG_L2ACTLR
749 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
750 // MISCREG_CBAR
751 bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")),
752 // MISCREG_HTTBR
753 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
754 // MISCREG_VTTBR
755 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
756 // MISCREG_CNTPCT
757 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
758 // MISCREG_CNTVCT
759 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
760 // MISCREG_CNTP_CVAL
761 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
762 // MISCREG_CNTP_CVAL_NS
763 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
764 // MISCREG_CNTP_CVAL_S
765 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
766 // MISCREG_CNTV_CVAL
767 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
768 // MISCREG_CNTVOFF
769 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
770 // MISCREG_CNTHP_CVAL
771 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
772 // MISCREG_CPUMERRSR
773 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
774 // MISCREG_L2MERRSR
775 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
776
777 // AArch64 registers (Op0=2)
778 // MISCREG_MDCCINT_EL1
779 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
780 // MISCREG_OSDTRRX_EL1
781 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
782 // MISCREG_MDSCR_EL1
783 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
784 // MISCREG_OSDTRTX_EL1
785 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
786 // MISCREG_OSECCR_EL1
787 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
788 // MISCREG_DBGBVR0_EL1
789 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
790 // MISCREG_DBGBVR1_EL1
791 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
792 // MISCREG_DBGBVR2_EL1
793 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
794 // MISCREG_DBGBVR3_EL1
795 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
796 // MISCREG_DBGBVR4_EL1
797 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
798 // MISCREG_DBGBVR5_EL1
799 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
800 // MISCREG_DBGBCR0_EL1
801 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
802 // MISCREG_DBGBCR1_EL1
803 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
804 // MISCREG_DBGBCR2_EL1
805 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
806 // MISCREG_DBGBCR3_EL1
807 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
808 // MISCREG_DBGBCR4_EL1
809 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
810 // MISCREG_DBGBCR5_EL1
811 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
812 // MISCREG_DBGWVR0_EL1
813 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
814 // MISCREG_DBGWVR1_EL1
815 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
816 // MISCREG_DBGWVR2_EL1
817 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
818 // MISCREG_DBGWVR3_EL1
819 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
820 // MISCREG_DBGWCR0_EL1
821 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
822 // MISCREG_DBGWCR1_EL1
823 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
824 // MISCREG_DBGWCR2_EL1
825 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
826 // MISCREG_DBGWCR3_EL1
827 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
828 // MISCREG_MDCCSR_EL0
829 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
830 // MISCREG_MDDTR_EL0
831 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
832 // MISCREG_MDDTRTX_EL0
833 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
834 // MISCREG_MDDTRRX_EL0
835 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
836 // MISCREG_DBGVCR32_EL2
837 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
838 // MISCREG_MDRAR_EL1
839 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
840 // MISCREG_OSLAR_EL1
841 bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")),
842 // MISCREG_OSLSR_EL1
843 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
844 // MISCREG_OSDLR_EL1
845 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
846 // MISCREG_DBGPRCR_EL1
847 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
848 // MISCREG_DBGCLAIMSET_EL1
849 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
850 // MISCREG_DBGCLAIMCLR_EL1
851 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
852 // MISCREG_DBGAUTHSTATUS_EL1
853 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
854 // MISCREG_TEECR32_EL1
855 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
856 // MISCREG_TEEHBR32_EL1
857 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
858
859 // AArch64 registers (Op0=1,3)
860 // MISCREG_MIDR_EL1
861 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
862 // MISCREG_MPIDR_EL1
863 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
864 // MISCREG_REVIDR_EL1
865 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
866 // MISCREG_ID_PFR0_EL1
867 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
868 // MISCREG_ID_PFR1_EL1
869 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
870 // MISCREG_ID_DFR0_EL1
871 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
872 // MISCREG_ID_AFR0_EL1
873 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
874 // MISCREG_ID_MMFR0_EL1
875 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
876 // MISCREG_ID_MMFR1_EL1
877 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
878 // MISCREG_ID_MMFR2_EL1
879 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
880 // MISCREG_ID_MMFR3_EL1
881 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
882 // MISCREG_ID_ISAR0_EL1
883 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
884 // MISCREG_ID_ISAR1_EL1
885 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
886 // MISCREG_ID_ISAR2_EL1
887 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
888 // MISCREG_ID_ISAR3_EL1
889 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
890 // MISCREG_ID_ISAR4_EL1
891 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
892 // MISCREG_ID_ISAR5_EL1
893 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
894 // MISCREG_MVFR0_EL1
895 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
896 // MISCREG_MVFR1_EL1
897 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
898 // MISCREG_MVFR2_EL1
899 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
900 // MISCREG_ID_AA64PFR0_EL1
901 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
902 // MISCREG_ID_AA64PFR1_EL1
903 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
904 // MISCREG_ID_AA64DFR0_EL1
905 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
906 // MISCREG_ID_AA64DFR1_EL1
907 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
908 // MISCREG_ID_AA64AFR0_EL1
909 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
910 // MISCREG_ID_AA64AFR1_EL1
911 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
912 // MISCREG_ID_AA64ISAR0_EL1
913 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
914 // MISCREG_ID_AA64ISAR1_EL1
915 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
916 // MISCREG_ID_AA64MMFR0_EL1
917 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
918 // MISCREG_ID_AA64MMFR1_EL1
919 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
920 // MISCREG_CCSIDR_EL1
921 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
922 // MISCREG_CLIDR_EL1
923 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
924 // MISCREG_AIDR_EL1
925 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
926 // MISCREG_CSSELR_EL1
927 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
928 // MISCREG_CTR_EL0
929 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
930 // MISCREG_DCZID_EL0
931 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
932 // MISCREG_VPIDR_EL2
933 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
934 // MISCREG_VMPIDR_EL2
935 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
936 // MISCREG_SCTLR_EL1
937 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
938 // MISCREG_ACTLR_EL1
939 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
940 // MISCREG_CPACR_EL1
941 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
942 // MISCREG_SCTLR_EL2
943 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
944 // MISCREG_ACTLR_EL2
945 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
946 // MISCREG_HCR_EL2
947 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
948 // MISCREG_MDCR_EL2
949 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
950 // MISCREG_CPTR_EL2
951 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
952 // MISCREG_HSTR_EL2
953 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
954 // MISCREG_HACR_EL2
955 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
956 // MISCREG_SCTLR_EL3
957 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
958 // MISCREG_ACTLR_EL3
959 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
960 // MISCREG_SCR_EL3
961 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
962 // MISCREG_SDER32_EL3
963 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
964 // MISCREG_CPTR_EL3
965 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
966 // MISCREG_MDCR_EL3
967 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
968 // MISCREG_TTBR0_EL1
969 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
970 // MISCREG_TTBR1_EL1
971 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
972 // MISCREG_TCR_EL1
973 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
974 // MISCREG_TTBR0_EL2
975 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
976 // MISCREG_TCR_EL2
977 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
978 // MISCREG_VTTBR_EL2
979 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
980 // MISCREG_VTCR_EL2
981 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
982 // MISCREG_TTBR0_EL3
983 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
984 // MISCREG_TCR_EL3
985 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
986 // MISCREG_DACR32_EL2
987 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
988 // MISCREG_SPSR_EL1
989 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
990 // MISCREG_ELR_EL1
991 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
992 // MISCREG_SP_EL0
993 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
994 // MISCREG_SPSEL
995 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
996 // MISCREG_CURRENTEL
997 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
998 // MISCREG_NZCV
999 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1000 // MISCREG_DAIF
1001 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1002 // MISCREG_FPCR
1003 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1004 // MISCREG_FPSR
1005 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1006 // MISCREG_DSPSR_EL0
1007 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1008 // MISCREG_DLR_EL0
1009 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1010 // MISCREG_SPSR_EL2
1011 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1012 // MISCREG_ELR_EL2
1013 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1014 // MISCREG_SP_EL1
1015 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1016 // MISCREG_SPSR_IRQ_AA64
1017 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1018 // MISCREG_SPSR_ABT_AA64
1019 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1020 // MISCREG_SPSR_UND_AA64
1021 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1022 // MISCREG_SPSR_FIQ_AA64
1023 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1024 // MISCREG_SPSR_EL3
1025 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1026 // MISCREG_ELR_EL3
1027 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1028 // MISCREG_SP_EL2
1029 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1030 // MISCREG_AFSR0_EL1
1031 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1032 // MISCREG_AFSR1_EL1
1033 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1034 // MISCREG_ESR_EL1
1035 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1036 // MISCREG_IFSR32_EL2
1037 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1038 // MISCREG_AFSR0_EL2
1039 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1040 // MISCREG_AFSR1_EL2
1041 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1042 // MISCREG_ESR_EL2
1043 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1044 // MISCREG_FPEXC32_EL2
1045 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1046 // MISCREG_AFSR0_EL3
1047 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1048 // MISCREG_AFSR1_EL3
1049 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1050 // MISCREG_ESR_EL3
1051 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1052 // MISCREG_FAR_EL1
1053 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1054 // MISCREG_FAR_EL2
1055 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1056 // MISCREG_HPFAR_EL2
1057 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1058 // MISCREG_FAR_EL3
1059 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1060 // MISCREG_IC_IALLUIS
1061 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1062 // MISCREG_PAR_EL1
1063 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1064 // MISCREG_IC_IALLU
1065 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1066 // MISCREG_DC_IVAC_Xt
1067 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1068 // MISCREG_DC_ISW_Xt
1069 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1070 // MISCREG_AT_S1E1R_Xt
1071 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1072 // MISCREG_AT_S1E1W_Xt
1073 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1074 // MISCREG_AT_S1E0R_Xt
1075 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1076 // MISCREG_AT_S1E0W_Xt
1077 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1078 // MISCREG_DC_CSW_Xt
1079 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1080 // MISCREG_DC_CISW_Xt
1081 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1082 // MISCREG_DC_ZVA_Xt
1083 bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")),
1084 // MISCREG_IC_IVAU_Xt
1085 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
1086 // MISCREG_DC_CVAC_Xt
1087 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1088 // MISCREG_DC_CVAU_Xt
1089 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1090 // MISCREG_DC_CIVAC_Xt
1091 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1092 // MISCREG_AT_S1E2R_Xt
1093 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1094 // MISCREG_AT_S1E2W_Xt
1095 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1096 // MISCREG_AT_S12E1R_Xt
1097 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1098 // MISCREG_AT_S12E1W_Xt
1099 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1100 // MISCREG_AT_S12E0R_Xt
1101 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1102 // MISCREG_AT_S12E0W_Xt
1103 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1104 // MISCREG_AT_S1E3R_Xt
1105 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1106 // MISCREG_AT_S1E3W_Xt
1107 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1108 // MISCREG_TLBI_VMALLE1IS
1109 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1110 // MISCREG_TLBI_VAE1IS_Xt
1111 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1112 // MISCREG_TLBI_ASIDE1IS_Xt
1113 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1114 // MISCREG_TLBI_VAAE1IS_Xt
1115 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1116 // MISCREG_TLBI_VALE1IS_Xt
1117 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1118 // MISCREG_TLBI_VAALE1IS_Xt
1119 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1120 // MISCREG_TLBI_VMALLE1
1121 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1122 // MISCREG_TLBI_VAE1_Xt
1123 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1124 // MISCREG_TLBI_ASIDE1_Xt
1125 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1126 // MISCREG_TLBI_VAAE1_Xt
1127 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1128 // MISCREG_TLBI_VALE1_Xt
1129 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1130 // MISCREG_TLBI_VAALE1_Xt
1131 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1132 // MISCREG_TLBI_IPAS2E1IS_Xt
1133 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1134 // MISCREG_TLBI_IPAS2LE1IS_Xt
1135 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1136 // MISCREG_TLBI_ALLE2IS
1137 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1138 // MISCREG_TLBI_VAE2IS_Xt
1139 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1140 // MISCREG_TLBI_ALLE1IS
1141 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1142 // MISCREG_TLBI_VALE2IS_Xt
1143 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1144 // MISCREG_TLBI_VMALLS12E1IS
1145 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1146 // MISCREG_TLBI_IPAS2E1_Xt
1147 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1148 // MISCREG_TLBI_IPAS2LE1_Xt
1149 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1150 // MISCREG_TLBI_ALLE2
1151 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1152 // MISCREG_TLBI_VAE2_Xt
1153 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1154 // MISCREG_TLBI_ALLE1
1155 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1156 // MISCREG_TLBI_VALE2_Xt
1157 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1158 // MISCREG_TLBI_VMALLS12E1
1159 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1160 // MISCREG_TLBI_ALLE3IS
1161 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1162 // MISCREG_TLBI_VAE3IS_Xt
1163 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1164 // MISCREG_TLBI_VALE3IS_Xt
1165 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1166 // MISCREG_TLBI_ALLE3
1167 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1168 // MISCREG_TLBI_VAE3_Xt
1169 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1170 // MISCREG_TLBI_VALE3_Xt
1171 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1172 // MISCREG_PMINTENSET_EL1
1173 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1174 // MISCREG_PMINTENCLR_EL1
1175 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1176 // MISCREG_PMCR_EL0
1177 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1178 // MISCREG_PMCNTENSET_EL0
1179 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1180 // MISCREG_PMCNTENCLR_EL0
1181 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1182 // MISCREG_PMOVSCLR_EL0
1183 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1184 // MISCREG_PMSWINC_EL0
1185 bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")),
1186 // MISCREG_PMSELR_EL0
1187 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1188 // MISCREG_PMCEID0_EL0
1189 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
1190 // MISCREG_PMCEID1_EL0
1191 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
1192 // MISCREG_PMCCNTR_EL0
1193 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1194 // MISCREG_PMXEVTYPER_EL0
1195 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1196 // MISCREG_PMCCFILTR_EL0
1197 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1198 // MISCREG_PMXEVCNTR_EL0
1199 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1200 // MISCREG_PMUSERENR_EL0
1201 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
1202 // MISCREG_PMOVSSET_EL0
1203 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1204 // MISCREG_MAIR_EL1
1205 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1206 // MISCREG_AMAIR_EL1
1207 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1208 // MISCREG_MAIR_EL2
1209 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1210 // MISCREG_AMAIR_EL2
1211 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1212 // MISCREG_MAIR_EL3
1213 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1214 // MISCREG_AMAIR_EL3
1215 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1216 // MISCREG_L2CTLR_EL1
1217 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1218 // MISCREG_L2ECTLR_EL1
1219 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1220 // MISCREG_VBAR_EL1
1221 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1222 // MISCREG_RVBAR_EL1
1223 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1224 // MISCREG_ISR_EL1
1225 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1226 // MISCREG_VBAR_EL2
1227 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1228 // MISCREG_RVBAR_EL2
1229 bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")),
1230 // MISCREG_VBAR_EL3
1231 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1232 // MISCREG_RVBAR_EL3
1233 bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")),
1234 // MISCREG_RMR_EL3
1235 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1236 // MISCREG_CONTEXTIDR_EL1
1237 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1238 // MISCREG_TPIDR_EL1
1239 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1240 // MISCREG_TPIDR_EL0
1241 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1242 // MISCREG_TPIDRRO_EL0
1243 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
1244 // MISCREG_TPIDR_EL2
1245 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1246 // MISCREG_TPIDR_EL3
1247 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1248 // MISCREG_CNTKCTL_EL1
1249 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1250 // MISCREG_CNTFRQ_EL0
1251 bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")),
1252 // MISCREG_CNTPCT_EL0
1253 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
1254 // MISCREG_CNTVCT_EL0
1255 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
1256 // MISCREG_CNTP_TVAL_EL0
1257 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1258 // MISCREG_CNTP_CTL_EL0
1259 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1260 // MISCREG_CNTP_CVAL_EL0
1261 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1262 // MISCREG_CNTV_TVAL_EL0
1263 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1264 // MISCREG_CNTV_CTL_EL0
1265 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1266 // MISCREG_CNTV_CVAL_EL0
1267 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1268 // MISCREG_PMEVCNTR0_EL0
1269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1270 // MISCREG_PMEVCNTR1_EL0
1271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1272 // MISCREG_PMEVCNTR2_EL0
1273 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1274 // MISCREG_PMEVCNTR3_EL0
1275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1276 // MISCREG_PMEVCNTR4_EL0
1277 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1278 // MISCREG_PMEVCNTR5_EL0
1279 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1280 // MISCREG_PMEVTYPER0_EL0
1281 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1282 // MISCREG_PMEVTYPER1_EL0
1283 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1284 // MISCREG_PMEVTYPER2_EL0
1285 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1286 // MISCREG_PMEVTYPER3_EL0
1287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1288 // MISCREG_PMEVTYPER4_EL0
1289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1290 // MISCREG_PMEVTYPER5_EL0
1291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1292 // MISCREG_CNTVOFF_EL2
1293 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1294 // MISCREG_CNTHCTL_EL2
1295 bitset<NUM_MISCREG_INFOS>(string("01111000000000000100")),
1296 // MISCREG_CNTHP_TVAL_EL2
1297 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1298 // MISCREG_CNTHP_CTL_EL2
1299 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1300 // MISCREG_CNTHP_CVAL_EL2
1301 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1302 // MISCREG_CNTPS_TVAL_EL1
1303 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1304 // MISCREG_CNTPS_CTL_EL1
1305 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1306 // MISCREG_CNTPS_CVAL_EL1
1307 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1308 // MISCREG_IL1DATA0_EL1
1309 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1310 // MISCREG_IL1DATA1_EL1
1311 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1312 // MISCREG_IL1DATA2_EL1
1313 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1314 // MISCREG_IL1DATA3_EL1
1315 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1316 // MISCREG_DL1DATA0_EL1
1317 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1318 // MISCREG_DL1DATA1_EL1
1319 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1320 // MISCREG_DL1DATA2_EL1
1321 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1322 // MISCREG_DL1DATA3_EL1
1323 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1324 // MISCREG_DL1DATA4_EL1
1325 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1326 // MISCREG_L2ACTLR_EL1
1327 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1328 // MISCREG_CPUACTLR_EL1
1329 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1330 // MISCREG_CPUECTLR_EL1
1331 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1332 // MISCREG_CPUMERRSR_EL1
1333 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1334 // MISCREG_L2MERRSR_EL1
1335 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
1336 // MISCREG_CBAR_EL1
1337 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1338 // MISCREG_CONTEXTIDR_EL2
1339 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1340
1341 // Dummy registers
1342 // MISCREG_NOP
1343 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1344 // MISCREG_RAZ
1345 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1346 // MISCREG_CP14_UNIMPL
1347 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1348 // MISCREG_CP15_UNIMPL
1349 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1350 // MISCREG_A64_UNIMPL
1351 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1352 // MISCREG_UNKNOWN
1353 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001"))
1354};
1355
1356MiscRegIndex
1357decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
1358{
1359 switch (crn) {
1360 case 0:
1361 switch (opc1) {
1362 case 0:
1363 switch (crm) {
1364 case 0:
1365 switch (opc2) {
1366 case 1:
1367 return MISCREG_CTR;
1368 case 2:
1369 return MISCREG_TCMTR;
1370 case 3:
1371 return MISCREG_TLBTR;
1372 case 5:
1373 return MISCREG_MPIDR;
1374 case 6:
1375 return MISCREG_REVIDR;
1376 default:
1377 return MISCREG_MIDR;
1378 }
1379 break;
1380 case 1:
1381 switch (opc2) {
1382 case 0:
1383 return MISCREG_ID_PFR0;
1384 case 1:
1385 return MISCREG_ID_PFR1;
1386 case 2:
1387 return MISCREG_ID_DFR0;
1388 case 3:
1389 return MISCREG_ID_AFR0;
1390 case 4:
1391 return MISCREG_ID_MMFR0;
1392 case 5:
1393 return MISCREG_ID_MMFR1;
1394 case 6:
1395 return MISCREG_ID_MMFR2;
1396 case 7:
1397 return MISCREG_ID_MMFR3;
1398 }
1399 break;
1400 case 2:
1401 switch (opc2) {
1402 case 0:
1403 return MISCREG_ID_ISAR0;
1404 case 1:
1405 return MISCREG_ID_ISAR1;
1406 case 2:
1407 return MISCREG_ID_ISAR2;
1408 case 3:
1409 return MISCREG_ID_ISAR3;
1410 case 4:
1411 return MISCREG_ID_ISAR4;
1412 case 5:
1413 return MISCREG_ID_ISAR5;
1414 case 6:
1415 case 7:
1416 return MISCREG_RAZ; // read as zero
1417 }
1418 break;
1419 default:
1420 return MISCREG_RAZ; // read as zero
1421 }
1422 break;
1423 case 1:
1424 if (crm == 0) {
1425 switch (opc2) {
1426 case 0:
1427 return MISCREG_CCSIDR;
1428 case 1:
1429 return MISCREG_CLIDR;
1430 case 7:
1431 return MISCREG_AIDR;
1432 }
1433 }
1434 break;
1435 case 2:
1436 if (crm == 0 && opc2 == 0) {
1437 return MISCREG_CSSELR;
1438 }
1439 break;
1440 case 4:
1441 if (crm == 0) {
1442 if (opc2 == 0)
1443 return MISCREG_VPIDR;
1444 else if (opc2 == 5)
1445 return MISCREG_VMPIDR;
1446 }
1447 break;
1448 }
1449 break;
1450 case 1:
1451 if (opc1 == 0) {
1452 if (crm == 0) {
1453 switch (opc2) {
1454 case 0:
1455 return MISCREG_SCTLR;
1456 case 1:
1457 return MISCREG_ACTLR;
1458 case 0x2:
1459 return MISCREG_CPACR;
1460 }
1461 } else if (crm == 1) {
1462 switch (opc2) {
1463 case 0:
1464 return MISCREG_SCR;
1465 case 1:
1466 return MISCREG_SDER;
1467 case 2:
1468 return MISCREG_NSACR;
1469 }
1470 }
1471 } else if (opc1 == 4) {
1472 if (crm == 0) {
1473 if (opc2 == 0)
1474 return MISCREG_HSCTLR;
1475 else if (opc2 == 1)
1476 return MISCREG_HACTLR;
1477 } else if (crm == 1) {
1478 switch (opc2) {
1479 case 0:
1480 return MISCREG_HCR;
1481 case 1:
1482 return MISCREG_HDCR;
1483 case 2:
1484 return MISCREG_HCPTR;
1485 case 3:
1486 return MISCREG_HSTR;
1487 case 7:
1488 return MISCREG_HACR;
1489 }
1490 }
1491 }
1492 break;
1493 case 2:
1494 if (opc1 == 0 && crm == 0) {
1495 switch (opc2) {
1496 case 0:
1497 return MISCREG_TTBR0;
1498 case 1:
1499 return MISCREG_TTBR1;
1500 case 2:
1501 return MISCREG_TTBCR;
1502 }
1503 } else if (opc1 == 4) {
1504 if (crm == 0 && opc2 == 2)
1505 return MISCREG_HTCR;
1506 else if (crm == 1 && opc2 == 2)
1507 return MISCREG_VTCR;
1508 }
1509 break;
1510 case 3:
1511 if (opc1 == 0 && crm == 0 && opc2 == 0) {
1512 return MISCREG_DACR;
1513 }
1514 break;
1515 case 5:
1516 if (opc1 == 0) {
1517 if (crm == 0) {
1518 if (opc2 == 0) {
1519 return MISCREG_DFSR;
1520 } else if (opc2 == 1) {
1521 return MISCREG_IFSR;
1522 }
1523 } else if (crm == 1) {
1524 if (opc2 == 0) {
1525 return MISCREG_ADFSR;
1526 } else if (opc2 == 1) {
1527 return MISCREG_AIFSR;
1528 }
1529 }
1530 } else if (opc1 == 4) {
1531 if (crm == 1) {
1532 if (opc2 == 0)
1533 return MISCREG_HADFSR;
1534 else if (opc2 == 1)
1535 return MISCREG_HAIFSR;
1536 } else if (crm == 2 && opc2 == 0) {
1537 return MISCREG_HSR;
1538 }
1539 }
1540 break;
1541 case 6:
1542 if (opc1 == 0 && crm == 0) {
1543 switch (opc2) {
1544 case 0:
1545 return MISCREG_DFAR;
1546 case 2:
1547 return MISCREG_IFAR;
1548 }
1549 } else if (opc1 == 4 && crm == 0) {
1550 switch (opc2) {
1551 case 0:
1552 return MISCREG_HDFAR;
1553 case 2:
1554 return MISCREG_HIFAR;
1555 case 4:
1556 return MISCREG_HPFAR;
1557 }
1558 }
1559 break;
1560 case 7:
1561 if (opc1 == 0) {
1562 switch (crm) {
1563 case 0:
1564 if (opc2 == 4) {
1565 return MISCREG_NOP;
1566 }
1567 break;
1568 case 1:
1569 switch (opc2) {
1570 case 0:
1571 return MISCREG_ICIALLUIS;
1572 case 6:
1573 return MISCREG_BPIALLIS;
1574 }
1575 break;
1576 case 4:
1577 if (opc2 == 0) {
1578 return MISCREG_PAR;
1579 }
1580 break;
1581 case 5:
1582 switch (opc2) {
1583 case 0:
1584 return MISCREG_ICIALLU;
1585 case 1:
1586 return MISCREG_ICIMVAU;
1587 case 4:
1588 return MISCREG_CP15ISB;
1589 case 6:
1590 return MISCREG_BPIALL;
1591 case 7:
1592 return MISCREG_BPIMVA;
1593 }
1594 break;
1595 case 6:
1596 if (opc2 == 1) {
1597 return MISCREG_DCIMVAC;
1598 } else if (opc2 == 2) {
1599 return MISCREG_DCISW;
1600 }
1601 break;
1602 case 8:
1603 switch (opc2) {
1604 case 0:
1605 return MISCREG_ATS1CPR;
1606 case 1:
1607 return MISCREG_ATS1CPW;
1608 case 2:
1609 return MISCREG_ATS1CUR;
1610 case 3:
1611 return MISCREG_ATS1CUW;
1612 case 4:
1613 return MISCREG_ATS12NSOPR;
1614 case 5:
1615 return MISCREG_ATS12NSOPW;
1616 case 6:
1617 return MISCREG_ATS12NSOUR;
1618 case 7:
1619 return MISCREG_ATS12NSOUW;
1620 }
1621 break;
1622 case 10:
1623 switch (opc2) {
1624 case 1:
1625 return MISCREG_DCCMVAC;
1626 case 2:
1627 return MISCREG_DCCSW;
1628 case 4:
1629 return MISCREG_CP15DSB;
1630 case 5:
1631 return MISCREG_CP15DMB;
1632 }
1633 break;
1634 case 11:
1635 if (opc2 == 1) {
1636 return MISCREG_DCCMVAU;
1637 }
1638 break;
1639 case 13:
1640 if (opc2 == 1) {
1641 return MISCREG_NOP;
1642 }
1643 break;
1644 case 14:
1645 if (opc2 == 1) {
1646 return MISCREG_DCCIMVAC;
1647 } else if (opc2 == 2) {
1648 return MISCREG_DCCISW;
1649 }
1650 break;
1651 }
1652 } else if (opc1 == 4 && crm == 8) {
1653 if (opc2 == 0)
1654 return MISCREG_ATS1HR;
1655 else if (opc2 == 1)
1656 return MISCREG_ATS1HW;
1657 }
1658 break;
1659 case 8:
1660 if (opc1 == 0) {
1661 switch (crm) {
1662 case 3:
1663 switch (opc2) {
1664 case 0:
1665 return MISCREG_TLBIALLIS;
1666 case 1:
1667 return MISCREG_TLBIMVAIS;
1668 case 2:
1669 return MISCREG_TLBIASIDIS;
1670 case 3:
1671 return MISCREG_TLBIMVAAIS;
1672 }
1673 break;
1674 case 5:
1675 switch (opc2) {
1676 case 0:
1677 return MISCREG_ITLBIALL;
1678 case 1:
1679 return MISCREG_ITLBIMVA;
1680 case 2:
1681 return MISCREG_ITLBIASID;
1682 }
1683 break;
1684 case 6:
1685 switch (opc2) {
1686 case 0:
1687 return MISCREG_DTLBIALL;
1688 case 1:
1689 return MISCREG_DTLBIMVA;
1690 case 2:
1691 return MISCREG_DTLBIASID;
1692 }
1693 break;
1694 case 7:
1695 switch (opc2) {
1696 case 0:
1697 return MISCREG_TLBIALL;
1698 case 1:
1699 return MISCREG_TLBIMVA;
1700 case 2:
1701 return MISCREG_TLBIASID;
1702 case 3:
1703 return MISCREG_TLBIMVAA;
1704 }
1705 break;
1706 }
1707 } else if (opc1 == 4) {
1708 if (crm == 3) {
1709 switch (opc2) {
1710 case 0:
1711 return MISCREG_TLBIALLHIS;
1712 case 1:
1713 return MISCREG_TLBIMVAHIS;
1714 case 4:
1715 return MISCREG_TLBIALLNSNHIS;
1716 }
1717 } else if (crm == 7) {
1718 switch (opc2) {
1719 case 0:
1720 return MISCREG_TLBIALLH;
1721 case 1:
1722 return MISCREG_TLBIMVAH;
1723 case 4:
1724 return MISCREG_TLBIALLNSNH;
1725 }
1726 }
1727 }
1728 break;
1729 case 9:
1730 if (opc1 == 0) {
1731 switch (crm) {
1732 case 12:
1733 switch (opc2) {
1734 case 0:
1735 return MISCREG_PMCR;
1736 case 1:
1737 return MISCREG_PMCNTENSET;
1738 case 2:
1739 return MISCREG_PMCNTENCLR;
1740 case 3:
1741 return MISCREG_PMOVSR;
1742 case 4:
1743 return MISCREG_PMSWINC;
1744 case 5:
1745 return MISCREG_PMSELR;
1746 case 6:
1747 return MISCREG_PMCEID0;
1748 case 7:
1749 return MISCREG_PMCEID1;
1750 }
1751 break;
1752 case 13:
1753 switch (opc2) {
1754 case 0:
1755 return MISCREG_PMCCNTR;
1756 case 1:
1757 // Selector is PMSELR.SEL
1758 return MISCREG_PMXEVTYPER_PMCCFILTR;
1759 case 2:
1760 return MISCREG_PMXEVCNTR;
1761 }
1762 break;
1763 case 14:
1764 switch (opc2) {
1765 case 0:
1766 return MISCREG_PMUSERENR;
1767 case 1:
1768 return MISCREG_PMINTENSET;
1769 case 2:
1770 return MISCREG_PMINTENCLR;
1771 case 3:
1772 return MISCREG_PMOVSSET;
1773 }
1774 break;
1775 }
1776 } else if (opc1 == 1) {
1777 switch (crm) {
1778 case 0:
1779 switch (opc2) {
1780 case 2: // L2CTLR, L2 Control Register
1781 return MISCREG_L2CTLR;
1782 case 3:
1783 return MISCREG_L2ECTLR;
1784 }
1785 break;
1786 break;
1787 }
1788 }
1789 break;
1790 case 10:
1791 if (opc1 == 0) {
1792 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1793 if (crm == 2) { // TEX Remap Registers
1794 if (opc2 == 0) {
1795 // Selector is TTBCR.EAE
1796 return MISCREG_PRRR_MAIR0;
1797 } else if (opc2 == 1) {
1798 // Selector is TTBCR.EAE
1799 return MISCREG_NMRR_MAIR1;
1800 }
1801 } else if (crm == 3) {
1802 if (opc2 == 0) {
1803 return MISCREG_AMAIR0;
1804 } else if (opc2 == 1) {
1805 return MISCREG_AMAIR1;
1806 }
1807 }
1808 } else if (opc1 == 4) {
1809 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1810 if (crm == 2) {
1811 if (opc2 == 0)
1812 return MISCREG_HMAIR0;
1813 else if (opc2 == 1)
1814 return MISCREG_HMAIR1;
1815 } else if (crm == 3) {
1816 if (opc2 == 0)
1817 return MISCREG_HAMAIR0;
1818 else if (opc2 == 1)
1819 return MISCREG_HAMAIR1;
1820 }
1821 }
1822 break;
1823 case 11:
1824 if (opc1 <=7) {
1825 switch (crm) {
1826 case 0:
1827 case 1:
1828 case 2:
1829 case 3:
1830 case 4:
1831 case 5:
1832 case 6:
1833 case 7:
1834 case 8:
1835 case 15:
1836 // Reserved for DMA operations for TCM access
1837 break;
1838 }
1839 }
1840 break;
1841 case 12:
1842 if (opc1 == 0) {
1843 if (crm == 0) {
1844 if (opc2 == 0) {
1845 return MISCREG_VBAR;
1846 } else if (opc2 == 1) {
1847 return MISCREG_MVBAR;
1848 }
1849 } else if (crm == 1) {
1850 if (opc2 == 0) {
1851 return MISCREG_ISR;
1852 }
1853 }
1854 } else if (opc1 == 4) {
1855 if (crm == 0 && opc2 == 0)
1856 return MISCREG_HVBAR;
1857 }
1858 break;
1859 case 13:
1860 if (opc1 == 0) {
1861 if (crm == 0) {
1862 switch (opc2) {
1863 case 0:
1864 return MISCREG_FCSEIDR;
1865 case 1:
1866 return MISCREG_CONTEXTIDR;
1867 case 2:
1868 return MISCREG_TPIDRURW;
1869 case 3:
1870 return MISCREG_TPIDRURO;
1871 case 4:
1872 return MISCREG_TPIDRPRW;
1873 }
1874 }
1875 } else if (opc1 == 4) {
1876 if (crm == 0 && opc2 == 2)
1877 return MISCREG_HTPIDR;
1878 }
1879 break;
1880 case 14:
1881 if (opc1 == 0) {
1882 switch (crm) {
1883 case 0:
1884 if (opc2 == 0)
1885 return MISCREG_CNTFRQ;
1886 break;
1887 case 1:
1888 if (opc2 == 0)
1889 return MISCREG_CNTKCTL;
1890 break;
1891 case 2:
1892 if (opc2 == 0)
1893 return MISCREG_CNTP_TVAL;
1894 else if (opc2 == 1)
1895 return MISCREG_CNTP_CTL;
1896 break;
1897 case 3:
1898 if (opc2 == 0)
1899 return MISCREG_CNTV_TVAL;
1900 else if (opc2 == 1)
1901 return MISCREG_CNTV_CTL;
1902 break;
1903 }
1904 } else if (opc1 == 4) {
1905 if (crm == 1 && opc2 == 0) {
1906 return MISCREG_CNTHCTL;
1907 } else if (crm == 2) {
1908 if (opc2 == 0)
1909 return MISCREG_CNTHP_TVAL;
1910 else if (opc2 == 1)
1911 return MISCREG_CNTHP_CTL;
1912 }
1913 }
1914 break;
1915 case 15:
1916 // Implementation defined
1917 return MISCREG_CP15_UNIMPL;
1918 }
1919 // Unrecognized register
1920 return MISCREG_CP15_UNIMPL;
1921}
1922
1923MiscRegIndex
1924decodeCP15Reg64(unsigned crm, unsigned opc1)
1925{
1926 switch (crm) {
1927 case 2:
1928 switch (opc1) {
1929 case 0:
1930 return MISCREG_TTBR0;
1931 case 1:
1932 return MISCREG_TTBR1;
1933 case 4:
1934 return MISCREG_HTTBR;
1935 case 6:
1936 return MISCREG_VTTBR;
1937 }
1938 break;
1939 case 7:
1940 if (opc1 == 0)
1941 return MISCREG_PAR;
1942 break;
1943 case 14:
1944 switch (opc1) {
1945 case 0:
1946 return MISCREG_CNTPCT;
1947 case 1:
1948 return MISCREG_CNTVCT;
1949 case 2:
1950 return MISCREG_CNTP_CVAL;
1951 case 3:
1952 return MISCREG_CNTV_CVAL;
1953 case 4:
1954 return MISCREG_CNTVOFF;
1955 case 6:
1956 return MISCREG_CNTHP_CVAL;
1957 }
1958 break;
1959 case 15:
1960 if (opc1 == 0)
1961 return MISCREG_CPUMERRSR;
1962 else if (opc1 == 1)
1963 return MISCREG_L2MERRSR;
1964 break;
1965 }
1966 // Unrecognized register
1967 return MISCREG_CP15_UNIMPL;
1968}
1969
1970bool
1971canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1972{
1973 bool secure = !scr.ns;
1974 bool canRead;
1975
1976 switch (cpsr.mode) {
1977 case MODE_USER:
1978 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1979 miscRegInfo[reg][MISCREG_USR_NS_RD];
1980 break;
1981 case MODE_FIQ:
1982 case MODE_IRQ:
1983 case MODE_SVC:
1984 case MODE_ABORT:
1985 case MODE_UNDEFINED:
1986 case MODE_SYSTEM:
1987 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1988 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1989 break;
1990 case MODE_MON:
1991 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1992 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1993 break;
1994 case MODE_HYP:
1995 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1996 break;
1997 default:
1998 panic("Unrecognized mode setting in CPSR.\n");
1999 }
2000 // can't do permissions checkes on the root of a banked pair of regs
2001 assert(!miscRegInfo[reg][MISCREG_BANKED]);
2002 return canRead;
2003}
2004
2005bool
2006canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2007{
2008 bool secure = !scr.ns;
2009 bool canWrite;
2010
2011 switch (cpsr.mode) {
2012 case MODE_USER:
2013 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
2014 miscRegInfo[reg][MISCREG_USR_NS_WR];
2015 break;
2016 case MODE_FIQ:
2017 case MODE_IRQ:
2018 case MODE_SVC:
2019 case MODE_ABORT:
2020 case MODE_UNDEFINED:
2021 case MODE_SYSTEM:
2022 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
2023 miscRegInfo[reg][MISCREG_PRI_NS_WR];
2024 break;
2025 case MODE_MON:
2026 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
2027 miscRegInfo[reg][MISCREG_MON_NS1_WR];
2028 break;
2029 case MODE_HYP:
2030 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
2031 break;
2032 default:
2033 panic("Unrecognized mode setting in CPSR.\n");
2034 }
2035 // can't do permissions checkes on the root of a banked pair of regs
2036 assert(!miscRegInfo[reg][MISCREG_BANKED]);
2037 return canWrite;
2038}
2039
2040int
2041flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
2042{
2043 SCR scr = tc->readMiscReg(MISCREG_SCR);
2044 return flattenMiscRegNsBanked(reg, tc, scr.ns);
2045}
2046
2047int
2048flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
2049{
2050 int reg_as_int = static_cast<int>(reg);
2051 if (miscRegInfo[reg][MISCREG_BANKED]) {
2052 reg_as_int += (ArmSystem::haveSecurity(tc) &&
2053 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
2054 }
2055 return reg_as_int;
2056}
2057
2058
2059/**
2060 * If the reg is a child reg of a banked set, then the parent is the last
2061 * banked one in the list. This is messy, and the wish is to eventually have
2062 * the bitmap replaced with a better data structure. the preUnflatten function
2063 * initializes a lookup table to speed up the search for these banked
2064 * registers.
2065 */
2066
2067int unflattenResultMiscReg[NUM_MISCREGS];
2068
2069void
2070preUnflattenMiscReg()
2071{
2072 int reg = -1;
2073 for (int i = 0 ; i < NUM_MISCREGS; i++){
2074 if (miscRegInfo[i][MISCREG_BANKED])
2075 reg = i;
2076 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
2077 unflattenResultMiscReg[i] = reg;
2078 else
2079 unflattenResultMiscReg[i] = i;
2080 // if this assert fails, no parent was found, and something is broken
2081 assert(unflattenResultMiscReg[i] > -1);
2082 }
2083}
2084
2085int
2086unflattenMiscReg(int reg)
2087{
2088 return unflattenResultMiscReg[reg];
2089}
2090
2091bool
2092canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2093{
2094 // Check for SP_EL0 access while SPSEL == 0
2095 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2096 return false;
2097
2098 // Check for RVBAR access
2099 if (reg == MISCREG_RVBAR_EL1) {
2100 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
2101 if (highest_el == EL2 || highest_el == EL3)
2102 return false;
2103 }
2104 if (reg == MISCREG_RVBAR_EL2) {
2105 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
2106 if (highest_el == EL3)
2107 return false;
2108 }
2109
2110 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2111
2112 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
2113 case EL0:
2114 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
2115 miscRegInfo[reg][MISCREG_USR_NS_RD];
2116 case EL1:
2117 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
2118 miscRegInfo[reg][MISCREG_PRI_NS_RD];
2119 case EL2:
2120 return miscRegInfo[reg][MISCREG_HYP_RD];
2121 case EL3:
2122 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
2123 miscRegInfo[reg][MISCREG_MON_NS1_RD];
2124 default:
2125 panic("Invalid exception level");
2126 }
2127}
2128
2129bool
2130canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2131{
2132 // Check for SP_EL0 access while SPSEL == 0
2133 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2134 return false;
2135 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
2136 if (reg == MISCREG_DAIF) {
2137 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2138 if (el == EL0 && !sctlr.uma)
2139 return false;
2140 }
2141 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
2142 // In syscall-emulation mode, this test is skipped and DCZVA is always
2143 // allowed at EL0
2144 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2145 if (el == EL0 && !sctlr.dze)
2146 return false;
2147 }
2148 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
2149 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2150 if (el == EL0 && !sctlr.uci)
2151 return false;
2152 }
2153
2154 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2155
2156 switch (el) {
2157 case EL0:
2158 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
2159 miscRegInfo[reg][MISCREG_USR_NS_WR];
2160 case EL1:
2161 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
2162 miscRegInfo[reg][MISCREG_PRI_NS_WR];
2163 case EL2:
2164 return miscRegInfo[reg][MISCREG_HYP_WR];
2165 case EL3:
2166 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
2167 miscRegInfo[reg][MISCREG_MON_NS1_WR];
2168 default:
2169 panic("Invalid exception level");
2170 }
2171}
2172
2173MiscRegIndex
2174decodeAArch64SysReg(unsigned op0, unsigned op1,
2175 unsigned crn, unsigned crm,
2176 unsigned op2)
2177{
2178 switch (op0) {
2179 case 1:
2180 switch (crn) {
2181 case 7:
2182 switch (op1) {
2183 case 0:
2184 switch (crm) {
2185 case 1:
2186 switch (op2) {
2187 case 0:
2188 return MISCREG_IC_IALLUIS;
2189 }
2190 break;
2191 case 5:
2192 switch (op2) {
2193 case 0:
2194 return MISCREG_IC_IALLU;
2195 }
2196 break;
2197 case 6:
2198 switch (op2) {
2199 case 1:
2200 return MISCREG_DC_IVAC_Xt;
2201 case 2:
2202 return MISCREG_DC_ISW_Xt;
2203 }
2204 break;
2205 case 8:
2206 switch (op2) {
2207 case 0:
2208 return MISCREG_AT_S1E1R_Xt;
2209 case 1:
2210 return MISCREG_AT_S1E1W_Xt;
2211 case 2:
2212 return MISCREG_AT_S1E0R_Xt;
2213 case 3:
2214 return MISCREG_AT_S1E0W_Xt;
2215 }
2216 break;
2217 case 10:
2218 switch (op2) {
2219 case 2:
2220 return MISCREG_DC_CSW_Xt;
2221 }
2222 break;
2223 case 14:
2224 switch (op2) {
2225 case 2:
2226 return MISCREG_DC_CISW_Xt;
2227 }
2228 break;
2229 }
2230 break;
2231 case 3:
2232 switch (crm) {
2233 case 4:
2234 switch (op2) {
2235 case 1:
2236 return MISCREG_DC_ZVA_Xt;
2237 }
2238 break;
2239 case 5:
2240 switch (op2) {
2241 case 1:
2242 return MISCREG_IC_IVAU_Xt;
2243 }
2244 break;
2245 case 10:
2246 switch (op2) {
2247 case 1:
2248 return MISCREG_DC_CVAC_Xt;
2249 }
2250 break;
2251 case 11:
2252 switch (op2) {
2253 case 1:
2254 return MISCREG_DC_CVAU_Xt;
2255 }
2256 break;
2257 case 14:
2258 switch (op2) {
2259 case 1:
2260 return MISCREG_DC_CIVAC_Xt;
2261 }
2262 break;
2263 }
2264 break;
2265 case 4:
2266 switch (crm) {
2267 case 8:
2268 switch (op2) {
2269 case 0:
2270 return MISCREG_AT_S1E2R_Xt;
2271 case 1:
2272 return MISCREG_AT_S1E2W_Xt;
2273 case 4:
2274 return MISCREG_AT_S12E1R_Xt;
2275 case 5:
2276 return MISCREG_AT_S12E1W_Xt;
2277 case 6:
2278 return MISCREG_AT_S12E0R_Xt;
2279 case 7:
2280 return MISCREG_AT_S12E0W_Xt;
2281 }
2282 break;
2283 }
2284 break;
2285 case 6:
2286 switch (crm) {
2287 case 8:
2288 switch (op2) {
2289 case 0:
2290 return MISCREG_AT_S1E3R_Xt;
2291 case 1:
2292 return MISCREG_AT_S1E3W_Xt;
2293 }
2294 break;
2295 }
2296 break;
2297 }
2298 break;
2299 case 8:
2300 switch (op1) {
2301 case 0:
2302 switch (crm) {
2303 case 3:
2304 switch (op2) {
2305 case 0:
2306 return MISCREG_TLBI_VMALLE1IS;
2307 case 1:
2308 return MISCREG_TLBI_VAE1IS_Xt;
2309 case 2:
2310 return MISCREG_TLBI_ASIDE1IS_Xt;
2311 case 3:
2312 return MISCREG_TLBI_VAAE1IS_Xt;
2313 case 5:
2314 return MISCREG_TLBI_VALE1IS_Xt;
2315 case 7:
2316 return MISCREG_TLBI_VAALE1IS_Xt;
2317 }
2318 break;
2319 case 7:
2320 switch (op2) {
2321 case 0:
2322 return MISCREG_TLBI_VMALLE1;
2323 case 1:
2324 return MISCREG_TLBI_VAE1_Xt;
2325 case 2:
2326 return MISCREG_TLBI_ASIDE1_Xt;
2327 case 3:
2328 return MISCREG_TLBI_VAAE1_Xt;
2329 case 5:
2330 return MISCREG_TLBI_VALE1_Xt;
2331 case 7:
2332 return MISCREG_TLBI_VAALE1_Xt;
2333 }
2334 break;
2335 }
2336 break;
2337 case 4:
2338 switch (crm) {
2339 case 0:
2340 switch (op2) {
2341 case 1:
2342 return MISCREG_TLBI_IPAS2E1IS_Xt;
2343 case 5:
2344 return MISCREG_TLBI_IPAS2LE1IS_Xt;
2345 }
2346 break;
2347 case 3:
2348 switch (op2) {
2349 case 0:
2350 return MISCREG_TLBI_ALLE2IS;
2351 case 1:
2352 return MISCREG_TLBI_VAE2IS_Xt;
2353 case 4:
2354 return MISCREG_TLBI_ALLE1IS;
2355 case 5:
2356 return MISCREG_TLBI_VALE2IS_Xt;
2357 case 6:
2358 return MISCREG_TLBI_VMALLS12E1IS;
2359 }
2360 break;
2361 case 4:
2362 switch (op2) {
2363 case 1:
2364 return MISCREG_TLBI_IPAS2E1_Xt;
2365 case 5:
2366 return MISCREG_TLBI_IPAS2LE1_Xt;
2367 }
2368 break;
2369 case 7:
2370 switch (op2) {
2371 case 0:
2372 return MISCREG_TLBI_ALLE2;
2373 case 1:
2374 return MISCREG_TLBI_VAE2_Xt;
2375 case 4:
2376 return MISCREG_TLBI_ALLE1;
2377 case 5:
2378 return MISCREG_TLBI_VALE2_Xt;
2379 case 6:
2380 return MISCREG_TLBI_VMALLS12E1;
2381 }
2382 break;
2383 }
2384 break;
2385 case 6:
2386 switch (crm) {
2387 case 3:
2388 switch (op2) {
2389 case 0:
2390 return MISCREG_TLBI_ALLE3IS;
2391 case 1:
2392 return MISCREG_TLBI_VAE3IS_Xt;
2393 case 5:
2394 return MISCREG_TLBI_VALE3IS_Xt;
2395 }
2396 break;
2397 case 7:
2398 switch (op2) {
2399 case 0:
2400 return MISCREG_TLBI_ALLE3;
2401 case 1:
2402 return MISCREG_TLBI_VAE3_Xt;
2403 case 5:
2404 return MISCREG_TLBI_VALE3_Xt;
2405 }
2406 break;
2407 }
2408 break;
2409 }
2410 break;
2411 }
2412 break;
2413 case 2:
2414 switch (crn) {
2415 case 0:
2416 switch (op1) {
2417 case 0:
2418 switch (crm) {
2419 case 0:
2420 switch (op2) {
2421 case 2:
2422 return MISCREG_OSDTRRX_EL1;
2423 case 4:
2424 return MISCREG_DBGBVR0_EL1;
2425 case 5:
2426 return MISCREG_DBGBCR0_EL1;
2427 case 6:
2428 return MISCREG_DBGWVR0_EL1;
2429 case 7:
2430 return MISCREG_DBGWCR0_EL1;
2431 }
2432 break;
2433 case 1:
2434 switch (op2) {
2435 case 4:
2436 return MISCREG_DBGBVR1_EL1;
2437 case 5:
2438 return MISCREG_DBGBCR1_EL1;
2439 case 6:
2440 return MISCREG_DBGWVR1_EL1;
2441 case 7:
2442 return MISCREG_DBGWCR1_EL1;
2443 }
2444 break;
2445 case 2:
2446 switch (op2) {
2447 case 0:
2448 return MISCREG_MDCCINT_EL1;
2449 case 2:
2450 return MISCREG_MDSCR_EL1;
2451 case 4:
2452 return MISCREG_DBGBVR2_EL1;
2453 case 5:
2454 return MISCREG_DBGBCR2_EL1;
2455 case 6:
2456 return MISCREG_DBGWVR2_EL1;
2457 case 7:
2458 return MISCREG_DBGWCR2_EL1;
2459 }
2460 break;
2461 case 3:
2462 switch (op2) {
2463 case 2:
2464 return MISCREG_OSDTRTX_EL1;
2465 case 4:
2466 return MISCREG_DBGBVR3_EL1;
2467 case 5:
2468 return MISCREG_DBGBCR3_EL1;
2469 case 6:
2470 return MISCREG_DBGWVR3_EL1;
2471 case 7:
2472 return MISCREG_DBGWCR3_EL1;
2473 }
2474 break;
2475 case 4:
2476 switch (op2) {
2477 case 4:
2478 return MISCREG_DBGBVR4_EL1;
2479 case 5:
2480 return MISCREG_DBGBCR4_EL1;
2481 }
2482 break;
2483 case 5:
2484 switch (op2) {
2485 case 4:
2486 return MISCREG_DBGBVR5_EL1;
2487 case 5:
2488 return MISCREG_DBGBCR5_EL1;
2489 }
2490 break;
2491 case 6:
2492 switch (op2) {
2493 case 2:
2494 return MISCREG_OSECCR_EL1;
2495 }
2496 break;
2497 }
2498 break;
2499 case 2:
2500 switch (crm) {
2501 case 0:
2502 switch (op2) {
2503 case 0:
2504 return MISCREG_TEECR32_EL1;
2505 }
2506 break;
2507 }
2508 break;
2509 case 3:
2510 switch (crm) {
2511 case 1:
2512 switch (op2) {
2513 case 0:
2514 return MISCREG_MDCCSR_EL0;
2515 }
2516 break;
2517 case 4:
2518 switch (op2) {
2519 case 0:
2520 return MISCREG_MDDTR_EL0;
2521 }
2522 break;
2523 case 5:
2524 switch (op2) {
2525 case 0:
2526 return MISCREG_MDDTRRX_EL0;
2527 }
2528 break;
2529 }
2530 break;
2531 case 4:
2532 switch (crm) {
2533 case 7:
2534 switch (op2) {
2535 case 0:
2536 return MISCREG_DBGVCR32_EL2;
2537 }
2538 break;
2539 }
2540 break;
2541 }
2542 break;
2543 case 1:
2544 switch (op1) {
2545 case 0:
2546 switch (crm) {
2547 case 0:
2548 switch (op2) {
2549 case 0:
2550 return MISCREG_MDRAR_EL1;
2551 case 4:
2552 return MISCREG_OSLAR_EL1;
2553 }
2554 break;
2555 case 1:
2556 switch (op2) {
2557 case 4:
2558 return MISCREG_OSLSR_EL1;
2559 }
2560 break;
2561 case 3:
2562 switch (op2) {
2563 case 4:
2564 return MISCREG_OSDLR_EL1;
2565 }
2566 break;
2567 case 4:
2568 switch (op2) {
2569 case 4:
2570 return MISCREG_DBGPRCR_EL1;
2571 }
2572 break;
2573 }
2574 break;
2575 case 2:
2576 switch (crm) {
2577 case 0:
2578 switch (op2) {
2579 case 0:
2580 return MISCREG_TEEHBR32_EL1;
2581 }
2582 break;
2583 }
2584 break;
2585 }
2586 break;
2587 case 7:
2588 switch (op1) {
2589 case 0:
2590 switch (crm) {
2591 case 8:
2592 switch (op2) {
2593 case 6:
2594 return MISCREG_DBGCLAIMSET_EL1;
2595 }
2596 break;
2597 case 9:
2598 switch (op2) {
2599 case 6:
2600 return MISCREG_DBGCLAIMCLR_EL1;
2601 }
2602 break;
2603 case 14:
2604 switch (op2) {
2605 case 6:
2606 return MISCREG_DBGAUTHSTATUS_EL1;
2607 }
2608 break;
2609 }
2610 break;
2611 }
2612 break;
2613 }
2614 break;
2615 case 3:
2616 switch (crn) {
2617 case 0:
2618 switch (op1) {
2619 case 0:
2620 switch (crm) {
2621 case 0:
2622 switch (op2) {
2623 case 0:
2624 return MISCREG_MIDR_EL1;
2625 case 5:
2626 return MISCREG_MPIDR_EL1;
2627 case 6:
2628 return MISCREG_REVIDR_EL1;
2629 }
2630 break;
2631 case 1:
2632 switch (op2) {
2633 case 0:
2634 return MISCREG_ID_PFR0_EL1;
2635 case 1:
2636 return MISCREG_ID_PFR1_EL1;
2637 case 2:
2638 return MISCREG_ID_DFR0_EL1;
2639 case 3:
2640 return MISCREG_ID_AFR0_EL1;
2641 case 4:
2642 return MISCREG_ID_MMFR0_EL1;
2643 case 5:
2644 return MISCREG_ID_MMFR1_EL1;
2645 case 6:
2646 return MISCREG_ID_MMFR2_EL1;
2647 case 7:
2648 return MISCREG_ID_MMFR3_EL1;
2649 }
2650 break;
2651 case 2:
2652 switch (op2) {
2653 case 0:
2654 return MISCREG_ID_ISAR0_EL1;
2655 case 1:
2656 return MISCREG_ID_ISAR1_EL1;
2657 case 2:
2658 return MISCREG_ID_ISAR2_EL1;
2659 case 3:
2660 return MISCREG_ID_ISAR3_EL1;
2661 case 4:
2662 return MISCREG_ID_ISAR4_EL1;
2663 case 5:
2664 return MISCREG_ID_ISAR5_EL1;
2665 }
2666 break;
2667 case 3:
2668 switch (op2) {
2669 case 0:
2670 return MISCREG_MVFR0_EL1;
2671 case 1:
2672 return MISCREG_MVFR1_EL1;
2673 case 2:
2674 return MISCREG_MVFR2_EL1;
2675 case 3 ... 7:
2676 return MISCREG_RAZ;
2677 }
2678 break;
2679 case 4:
2680 switch (op2) {
2681 case 0:
2682 return MISCREG_ID_AA64PFR0_EL1;
2683 case 1:
2684 return MISCREG_ID_AA64PFR1_EL1;
2685 case 2 ... 7:
2686 return MISCREG_RAZ;
2687 }
2688 break;
2689 case 5:
2690 switch (op2) {
2691 case 0:
2692 return MISCREG_ID_AA64DFR0_EL1;
2693 case 1:
2694 return MISCREG_ID_AA64DFR1_EL1;
2695 case 4:
2696 return MISCREG_ID_AA64AFR0_EL1;
2697 case 5:
2698 return MISCREG_ID_AA64AFR1_EL1;
2699 case 2:
2700 case 3:
2701 case 6:
2702 case 7:
2703 return MISCREG_RAZ;
2704 }
2705 break;
2706 case 6:
2707 switch (op2) {
2708 case 0:
2709 return MISCREG_ID_AA64ISAR0_EL1;
2710 case 1:
2711 return MISCREG_ID_AA64ISAR1_EL1;
2712 case 2 ... 7:
2713 return MISCREG_RAZ;
2714 }
2715 break;
2716 case 7:
2717 switch (op2) {
2718 case 0:
2719 return MISCREG_ID_AA64MMFR0_EL1;
2720 case 1:
2721 return MISCREG_ID_AA64MMFR1_EL1;
2722 case 2 ... 7:
2723 return MISCREG_RAZ;
2724 }
2725 break;
2726 }
2727 break;
2728 case 1:
2729 switch (crm) {
2730 case 0:
2731 switch (op2) {
2732 case 0:
2733 return MISCREG_CCSIDR_EL1;
2734 case 1:
2735 return MISCREG_CLIDR_EL1;
2736 case 7:
2737 return MISCREG_AIDR_EL1;
2738 }
2739 break;
2740 }
2741 break;
2742 case 2:
2743 switch (crm) {
2744 case 0:
2745 switch (op2) {
2746 case 0:
2747 return MISCREG_CSSELR_EL1;
2748 }
2749 break;
2750 }
2751 break;
2752 case 3:
2753 switch (crm) {
2754 case 0:
2755 switch (op2) {
2756 case 1:
2757 return MISCREG_CTR_EL0;
2758 case 7:
2759 return MISCREG_DCZID_EL0;
2760 }
2761 break;
2762 }
2763 break;
2764 case 4:
2765 switch (crm) {
2766 case 0:
2767 switch (op2) {
2768 case 0:
2769 return MISCREG_VPIDR_EL2;
2770 case 5:
2771 return MISCREG_VMPIDR_EL2;
2772 }
2773 break;
2774 }
2775 break;
2776 }
2777 break;
2778 case 1:
2779 switch (op1) {
2780 case 0:
2781 switch (crm) {
2782 case 0:
2783 switch (op2) {
2784 case 0:
2785 return MISCREG_SCTLR_EL1;
2786 case 1:
2787 return MISCREG_ACTLR_EL1;
2788 case 2:
2789 return MISCREG_CPACR_EL1;
2790 }
2791 break;
2792 }
2793 break;
2794 case 4:
2795 switch (crm) {
2796 case 0:
2797 switch (op2) {
2798 case 0:
2799 return MISCREG_SCTLR_EL2;
2800 case 1:
2801 return MISCREG_ACTLR_EL2;
2802 }
2803 break;
2804 case 1:
2805 switch (op2) {
2806 case 0:
2807 return MISCREG_HCR_EL2;
2808 case 1:
2809 return MISCREG_MDCR_EL2;
2810 case 2:
2811 return MISCREG_CPTR_EL2;
2812 case 3:
2813 return MISCREG_HSTR_EL2;
2814 case 7:
2815 return MISCREG_HACR_EL2;
2816 }
2817 break;
2818 }
2819 break;
2820 case 6:
2821 switch (crm) {
2822 case 0:
2823 switch (op2) {
2824 case 0:
2825 return MISCREG_SCTLR_EL3;
2826 case 1:
2827 return MISCREG_ACTLR_EL3;
2828 }
2829 break;
2830 case 1:
2831 switch (op2) {
2832 case 0:
2833 return MISCREG_SCR_EL3;
2834 case 1:
2835 return MISCREG_SDER32_EL3;
2836 case 2:
2837 return MISCREG_CPTR_EL3;
2838 }
2839 break;
2840 case 3:
2841 switch (op2) {
2842 case 1:
2843 return MISCREG_MDCR_EL3;
2844 }
2845 break;
2846 }
2847 break;
2848 }
2849 break;
2850 case 2:
2851 switch (op1) {
2852 case 0:
2853 switch (crm) {
2854 case 0:
2855 switch (op2) {
2856 case 0:
2857 return MISCREG_TTBR0_EL1;
2858 case 1:
2859 return MISCREG_TTBR1_EL1;
2860 case 2:
2861 return MISCREG_TCR_EL1;
2862 }
2863 break;
2864 }
2865 break;
2866 case 4:
2867 switch (crm) {
2868 case 0:
2869 switch (op2) {
2870 case 0:
2871 return MISCREG_TTBR0_EL2;
2872 case 2:
2873 return MISCREG_TCR_EL2;
2874 }
2875 break;
2876 case 1:
2877 switch (op2) {
2878 case 0:
2879 return MISCREG_VTTBR_EL2;
2880 case 2:
2881 return MISCREG_VTCR_EL2;
2882 }
2883 break;
2884 }
2885 break;
2886 case 6:
2887 switch (crm) {
2888 case 0:
2889 switch (op2) {
2890 case 0:
2891 return MISCREG_TTBR0_EL3;
2892 case 2:
2893 return MISCREG_TCR_EL3;
2894 }
2895 break;
2896 }
2897 break;
2898 }
2899 break;
2900 case 3:
2901 switch (op1) {
2902 case 4:
2903 switch (crm) {
2904 case 0:
2905 switch (op2) {
2906 case 0:
2907 return MISCREG_DACR32_EL2;
2908 }
2909 break;
2910 }
2911 break;
2912 }
2913 break;
2914 case 4:
2915 switch (op1) {
2916 case 0:
2917 switch (crm) {
2918 case 0:
2919 switch (op2) {
2920 case 0:
2921 return MISCREG_SPSR_EL1;
2922 case 1:
2923 return MISCREG_ELR_EL1;
2924 }
2925 break;
2926 case 1:
2927 switch (op2) {
2928 case 0:
2929 return MISCREG_SP_EL0;
2930 }
2931 break;
2932 case 2:
2933 switch (op2) {
2934 case 0:
2935 return MISCREG_SPSEL;
2936 case 2:
2937 return MISCREG_CURRENTEL;
2938 }
2939 break;
2940 }
2941 break;
2942 case 3:
2943 switch (crm) {
2944 case 2:
2945 switch (op2) {
2946 case 0:
2947 return MISCREG_NZCV;
2948 case 1:
2949 return MISCREG_DAIF;
2950 }
2951 break;
2952 case 4:
2953 switch (op2) {
2954 case 0:
2955 return MISCREG_FPCR;
2956 case 1:
2957 return MISCREG_FPSR;
2958 }
2959 break;
2960 case 5:
2961 switch (op2) {
2962 case 0:
2963 return MISCREG_DSPSR_EL0;
2964 case 1:
2965 return MISCREG_DLR_EL0;
2966 }
2967 break;
2968 }
2969 break;
2970 case 4:
2971 switch (crm) {
2972 case 0:
2973 switch (op2) {
2974 case 0:
2975 return MISCREG_SPSR_EL2;
2976 case 1:
2977 return MISCREG_ELR_EL2;
2978 }
2979 break;
2980 case 1:
2981 switch (op2) {
2982 case 0:
2983 return MISCREG_SP_EL1;
2984 }
2985 break;
2986 case 3:
2987 switch (op2) {
2988 case 0:
2989 return MISCREG_SPSR_IRQ_AA64;
2990 case 1:
2991 return MISCREG_SPSR_ABT_AA64;
2992 case 2:
2993 return MISCREG_SPSR_UND_AA64;
2994 case 3:
2995 return MISCREG_SPSR_FIQ_AA64;
2996 }
2997 break;
2998 }
2999 break;
3000 case 6:
3001 switch (crm) {
3002 case 0:
3003 switch (op2) {
3004 case 0:
3005 return MISCREG_SPSR_EL3;
3006 case 1:
3007 return MISCREG_ELR_EL3;
3008 }
3009 break;
3010 case 1:
3011 switch (op2) {
3012 case 0:
3013 return MISCREG_SP_EL2;
3014 }
3015 break;
3016 }
3017 break;
3018 }
3019 break;
3020 case 5:
3021 switch (op1) {
3022 case 0:
3023 switch (crm) {
3024 case 1:
3025 switch (op2) {
3026 case 0:
3027 return MISCREG_AFSR0_EL1;
3028 case 1:
3029 return MISCREG_AFSR1_EL1;
3030 }
3031 break;
3032 case 2:
3033 switch (op2) {
3034 case 0:
3035 return MISCREG_ESR_EL1;
3036 }
3037 break;
3038 }
3039 break;
3040 case 4:
3041 switch (crm) {
3042 case 0:
3043 switch (op2) {
3044 case 1:
3045 return MISCREG_IFSR32_EL2;
3046 }
3047 break;
3048 case 1:
3049 switch (op2) {
3050 case 0:
3051 return MISCREG_AFSR0_EL2;
3052 case 1:
3053 return MISCREG_AFSR1_EL2;
3054 }
3055 break;
3056 case 2:
3057 switch (op2) {
3058 case 0:
3059 return MISCREG_ESR_EL2;
3060 }
3061 break;
3062 case 3:
3063 switch (op2) {
3064 case 0:
3065 return MISCREG_FPEXC32_EL2;
3066 }
3067 break;
3068 }
3069 break;
3070 case 6:
3071 switch (crm) {
3072 case 1:
3073 switch (op2) {
3074 case 0:
3075 return MISCREG_AFSR0_EL3;
3076 case 1:
3077 return MISCREG_AFSR1_EL3;
3078 }
3079 break;
3080 case 2:
3081 switch (op2) {
3082 case 0:
3083 return MISCREG_ESR_EL3;
3084 }
3085 break;
3086 }
3087 break;
3088 }
3089 break;
3090 case 6:
3091 switch (op1) {
3092 case 0:
3093 switch (crm) {
3094 case 0:
3095 switch (op2) {
3096 case 0:
3097 return MISCREG_FAR_EL1;
3098 }
3099 break;
3100 }
3101 break;
3102 case 4:
3103 switch (crm) {
3104 case 0:
3105 switch (op2) {
3106 case 0:
3107 return MISCREG_FAR_EL2;
3108 case 4:
3109 return MISCREG_HPFAR_EL2;
3110 }
3111 break;
3112 }
3113 break;
3114 case 6:
3115 switch (crm) {
3116 case 0:
3117 switch (op2) {
3118 case 0:
3119 return MISCREG_FAR_EL3;
3120 }
3121 break;
3122 }
3123 break;
3124 }
3125 break;
3126 case 7:
3127 switch (op1) {
3128 case 0:
3129 switch (crm) {
3130 case 4:
3131 switch (op2) {
3132 case 0:
3133 return MISCREG_PAR_EL1;
3134 }
3135 break;
3136 }
3137 break;
3138 }
3139 break;
3140 case 9:
3141 switch (op1) {
3142 case 0:
3143 switch (crm) {
3144 case 14:
3145 switch (op2) {
3146 case 1:
3147 return MISCREG_PMINTENSET_EL1;
3148 case 2:
3149 return MISCREG_PMINTENCLR_EL1;
3150 }
3151 break;
3152 }
3153 break;
3154 case 3:
3155 switch (crm) {
3156 case 12:
3157 switch (op2) {
3158 case 0:
3159 return MISCREG_PMCR_EL0;
3160 case 1:
3161 return MISCREG_PMCNTENSET_EL0;
3162 case 2:
3163 return MISCREG_PMCNTENCLR_EL0;
3164 case 3:
3165 return MISCREG_PMOVSCLR_EL0;
3166 case 4:
3167 return MISCREG_PMSWINC_EL0;
3168 case 5:
3169 return MISCREG_PMSELR_EL0;
3170 case 6:
3171 return MISCREG_PMCEID0_EL0;
3172 case 7:
3173 return MISCREG_PMCEID1_EL0;
3174 }
3175 break;
3176 case 13:
3177 switch (op2) {
3178 case 0:
3179 return MISCREG_PMCCNTR_EL0;
3180 case 1:
3181 return MISCREG_PMXEVTYPER_EL0;
3182 case 2:
3183 return MISCREG_PMXEVCNTR_EL0;
3184 }
3185 break;
3186 case 14:
3187 switch (op2) {
3188 case 0:
3189 return MISCREG_PMUSERENR_EL0;
3190 case 3:
3191 return MISCREG_PMOVSSET_EL0;
3192 }
3193 break;
3194 }
3195 break;
3196 }
3197 break;
3198 case 10:
3199 switch (op1) {
3200 case 0:
3201 switch (crm) {
3202 case 2:
3203 switch (op2) {
3204 case 0:
3205 return MISCREG_MAIR_EL1;
3206 }
3207 break;
3208 case 3:
3209 switch (op2) {
3210 case 0:
3211 return MISCREG_AMAIR_EL1;
3212 }
3213 break;
3214 }
3215 break;
3216 case 4:
3217 switch (crm) {
3218 case 2:
3219 switch (op2) {
3220 case 0:
3221 return MISCREG_MAIR_EL2;
3222 }
3223 break;
3224 case 3:
3225 switch (op2) {
3226 case 0:
3227 return MISCREG_AMAIR_EL2;
3228 }
3229 break;
3230 }
3231 break;
3232 case 6:
3233 switch (crm) {
3234 case 2:
3235 switch (op2) {
3236 case 0:
3237 return MISCREG_MAIR_EL3;
3238 }
3239 break;
3240 case 3:
3241 switch (op2) {
3242 case 0:
3243 return MISCREG_AMAIR_EL3;
3244 }
3245 break;
3246 }
3247 break;
3248 }
3249 break;
3250 case 11:
3251 switch (op1) {
3252 case 1:
3253 switch (crm) {
3254 case 0:
3255 switch (op2) {
3256 case 2:
3257 return MISCREG_L2CTLR_EL1;
3258 case 3:
3259 return MISCREG_L2ECTLR_EL1;
3260 }
3261 break;
3262 }
3263 break;
3264 }
3265 break;
3266 case 12:
3267 switch (op1) {
3268 case 0:
3269 switch (crm) {
3270 case 0:
3271 switch (op2) {
3272 case 0:
3273 return MISCREG_VBAR_EL1;
3274 case 1:
3275 return MISCREG_RVBAR_EL1;
3276 }
3277 break;
3278 case 1:
3279 switch (op2) {
3280 case 0:
3281 return MISCREG_ISR_EL1;
3282 }
3283 break;
3284 }
3285 break;
3286 case 4:
3287 switch (crm) {
3288 case 0:
3289 switch (op2) {
3290 case 0:
3291 return MISCREG_VBAR_EL2;
3292 case 1:
3293 return MISCREG_RVBAR_EL2;
3294 }
3295 break;
3296 }
3297 break;
3298 case 6:
3299 switch (crm) {
3300 case 0:
3301 switch (op2) {
3302 case 0:
3303 return MISCREG_VBAR_EL3;
3304 case 1:
3305 return MISCREG_RVBAR_EL3;
3306 case 2:
3307 return MISCREG_RMR_EL3;
3308 }
3309 break;
3310 }
3311 break;
3312 }
3313 break;
3314 case 13:
3315 switch (op1) {
3316 case 0:
3317 switch (crm) {
3318 case 0:
3319 switch (op2) {
3320 case 1:
3321 return MISCREG_CONTEXTIDR_EL1;
3322 case 4:
3323 return MISCREG_TPIDR_EL1;
3324 }
3325 break;
3326 }
3327 break;
3328 case 3:
3329 switch (crm) {
3330 case 0:
3331 switch (op2) {
3332 case 2:
3333 return MISCREG_TPIDR_EL0;
3334 case 3:
3335 return MISCREG_TPIDRRO_EL0;
3336 }
3337 break;
3338 }
3339 break;
3340 case 4:
3341 switch (crm) {
3342 case 0:
3343 switch (op2) {
3344 case 1:
3345 return MISCREG_CONTEXTIDR_EL2;
3346 case 2:
3347 return MISCREG_TPIDR_EL2;
3348 }
3349 break;
3350 }
3351 break;
3352 case 6:
3353 switch (crm) {
3354 case 0:
3355 switch (op2) {
3356 case 2:
3357 return MISCREG_TPIDR_EL3;
3358 }
3359 break;
3360 }
3361 break;
3362 }
3363 break;
3364 case 14:
3365 switch (op1) {
3366 case 0:
3367 switch (crm) {
3368 case 1:
3369 switch (op2) {
3370 case 0:
3371 return MISCREG_CNTKCTL_EL1;
3372 }
3373 break;
3374 }
3375 break;
3376 case 3:
3377 switch (crm) {
3378 case 0:
3379 switch (op2) {
3380 case 0:
3381 return MISCREG_CNTFRQ_EL0;
3382 case 1:
3383 return MISCREG_CNTPCT_EL0;
3384 case 2:
3385 return MISCREG_CNTVCT_EL0;
3386 }
3387 break;
3388 case 2:
3389 switch (op2) {
3390 case 0:
3391 return MISCREG_CNTP_TVAL_EL0;
3392 case 1:
3393 return MISCREG_CNTP_CTL_EL0;
3394 case 2:
3395 return MISCREG_CNTP_CVAL_EL0;
3396 }
3397 break;
3398 case 3:
3399 switch (op2) {
3400 case 0:
3401 return MISCREG_CNTV_TVAL_EL0;
3402 case 1:
3403 return MISCREG_CNTV_CTL_EL0;
3404 case 2:
3405 return MISCREG_CNTV_CVAL_EL0;
3406 }
3407 break;
3408 case 8:
3409 switch (op2) {
3410 case 0:
3411 return MISCREG_PMEVCNTR0_EL0;
3412 case 1:
3413 return MISCREG_PMEVCNTR1_EL0;
3414 case 2:
3415 return MISCREG_PMEVCNTR2_EL0;
3416 case 3:
3417 return MISCREG_PMEVCNTR3_EL0;
3418 case 4:
3419 return MISCREG_PMEVCNTR4_EL0;
3420 case 5:
3421 return MISCREG_PMEVCNTR5_EL0;
3422 }
3423 break;
3424 case 12:
3425 switch (op2) {
3426 case 0:
3427 return MISCREG_PMEVTYPER0_EL0;
3428 case 1:
3429 return MISCREG_PMEVTYPER1_EL0;
3430 case 2:
3431 return MISCREG_PMEVTYPER2_EL0;
3432 case 3:
3433 return MISCREG_PMEVTYPER3_EL0;
3434 case 4:
3435 return MISCREG_PMEVTYPER4_EL0;
3436 case 5:
3437 return MISCREG_PMEVTYPER5_EL0;
3438 }
3439 break;
3440 case 15:
3441 switch (op2) {
3442 case 7:
3443 return MISCREG_PMCCFILTR_EL0;
3444 }
3445 }
3446 break;
3447 case 4:
3448 switch (crm) {
3449 case 0:
3450 switch (op2) {
3451 case 3:
3452 return MISCREG_CNTVOFF_EL2;
3453 }
3454 break;
3455 case 1:
3456 switch (op2) {
3457 case 0:
3458 return MISCREG_CNTHCTL_EL2;
3459 }
3460 break;
3461 case 2:
3462 switch (op2) {
3463 case 0:
3464 return MISCREG_CNTHP_TVAL_EL2;
3465 case 1:
3466 return MISCREG_CNTHP_CTL_EL2;
3467 case 2:
3468 return MISCREG_CNTHP_CVAL_EL2;
3469 }
3470 break;
3471 }
3472 break;
3473 case 7:
3474 switch (crm) {
3475 case 2:
3476 switch (op2) {
3477 case 0:
3478 return MISCREG_CNTPS_TVAL_EL1;
3479 case 1:
3480 return MISCREG_CNTPS_CTL_EL1;
3481 case 2:
3482 return MISCREG_CNTPS_CVAL_EL1;
3483 }
3484 break;
3485 }
3486 break;
3487 }
3488 break;
3489 case 15:
3490 switch (op1) {
3491 case 0:
3492 switch (crm) {
3493 case 0:
3494 switch (op2) {
3495 case 0:
3496 return MISCREG_IL1DATA0_EL1;
3497 case 1:
3498 return MISCREG_IL1DATA1_EL1;
3499 case 2:
3500 return MISCREG_IL1DATA2_EL1;
3501 case 3:
3502 return MISCREG_IL1DATA3_EL1;
3503 }
3504 break;
3505 case 1:
3506 switch (op2) {
3507 case 0:
3508 return MISCREG_DL1DATA0_EL1;
3509 case 1:
3510 return MISCREG_DL1DATA1_EL1;
3511 case 2:
3512 return MISCREG_DL1DATA2_EL1;
3513 case 3:
3514 return MISCREG_DL1DATA3_EL1;
3515 case 4:
3516 return MISCREG_DL1DATA4_EL1;
3517 }
3518 break;
3519 }
3520 break;
3521 case 1:
3522 switch (crm) {
3523 case 0:
3524 switch (op2) {
3525 case 0:
3526 return MISCREG_L2ACTLR_EL1;
3527 }
3528 break;
3529 case 2:
3530 switch (op2) {
3531 case 0:
3532 return MISCREG_CPUACTLR_EL1;
3533 case 1:
3534 return MISCREG_CPUECTLR_EL1;
3535 case 2:
3536 return MISCREG_CPUMERRSR_EL1;
3537 case 3:
3538 return MISCREG_L2MERRSR_EL1;
3539 }
3540 break;
3541 case 3:
3542 switch (op2) {
3543 case 0:
3544 return MISCREG_CBAR_EL1;
3545
3546 }
3547 break;
3548 }
3549 break;
3550 }
3551 break;
3552 }
3553 break;
3554 }
3555
3556 return MISCREG_UNKNOWN;
3557}
3558
3559} // namespace ArmISA