1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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2077 switch (op2) {
2078 case 2:
2079 return MISCREG_L2CTLR_EL1;
2080 case 3:
2081 return MISCREG_L2ECTLR_EL1;
2082 }
2083 break;
2084 }
2085 M5_FALLTHROUGH;
2086 default:
2087 // S3_<op1>_11_<Cm>_<op2>
2088 return MISCREG_IMPDEF_UNIMPL;
2089 }
2090 M5_UNREACHABLE;
2091 case 12:
2092 switch (op1) {
2093 case 0:
2094 switch (crm) {
2095 case 0:
2096 switch (op2) {
2097 case 0:
2098 return MISCREG_VBAR_EL1;

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2368 case 0:
2369 return MISCREG_CBAR_EL1;
2370
2371 }
2372 break;
2373 }
2374 break;
2375 }
2376 // S3_<op1>_15_<Cm>_<op2>
2377 return MISCREG_IMPDEF_UNIMPL;
2378 }
2379 break;
2380 }
2381
2382 return MISCREG_UNKNOWN;
2383}
2384
2385bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below

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