29c29,30
< * Authors: Steve Reinhardt
---
> * Authors: Ali Saidi
> * Steve Reinhardt
41a43
> #include "arch/arm/miscregs.hh"
50a53,54
> xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
> xc->setMiscReg(MISCREG_LOCKFLAG, true);
57a62,89
> if (req->isSwap())
> return true;
>
> // Verify that the lock flag is still set and the address
> // is correct
> bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
> Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
> if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
> // Lock flag not set or addr mismatch in CPU;
> // don't even bother sending to memory system
> req->setExtraData(0);
> xc->setMiscReg(MISCREG_LOCKFLAG, false);
> // the rest of this code is not architectural;
> // it's just a debugging aid to help detect
> // livelock by warning on long sequences of failed
> // store conditionals
> int stCondFailures = xc->readStCondFailures();
> stCondFailures++;
> xc->setStCondFailures(stCondFailures);
> if (stCondFailures % 100000 == 0) {
> warn("context %d: %d consecutive "
> "store conditional failures\n",
> xc->contextId(), stCondFailures);
> }
>
> // store conditional failed already, so don't issue it to mem
> return false;
> }