3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Steve Reinhardt
43 * Stephen Hines
44 */
45
46#ifndef __ARCH_ARM_LOCKED_MEM_HH__
47#define __ARCH_ARM_LOCKED_MEM_HH__
48
49/**
50 * @file
51 *
52 * ISA-specific helper functions for locked memory accesses.
53 */
54
55#include "arch/arm/miscregs.hh"
56#include "arch/arm/isa_traits.hh"
57#include "debug/LLSC.hh"
58#include "mem/packet.hh"
59#include "mem/request.hh"
60
61namespace ArmISA
62{
63template <class XC>
64inline void
65handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
66{
67 // Should only every see invalidations / direct writes
68 assert(pkt->isInvalidate() || pkt->isWrite());
69
70 DPRINTF(LLSC,"%s: handling snoop for address: %#x locked: %d\n",
71 xc->getCpuPtr()->name(),pkt->getAddr(),
72 xc->readMiscReg(MISCREG_LOCKFLAG));
73 if (!xc->readMiscReg(MISCREG_LOCKFLAG))
74 return;
75
76 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
77 // If no caches are attached, the snoop address always needs to be masked
78 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
79
80 DPRINTF(LLSC,"%s: handling snoop for address: %#x locked addr: %#x\n",
81 xc->getCpuPtr()->name(),snoop_addr, locked_addr);
82 if (locked_addr == snoop_addr) {
83 DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
84 xc->getCpuPtr()->name());
85 xc->setMiscReg(MISCREG_LOCKFLAG, false);
86 // Implement ARMv8 WFE/SEV semantics
87 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
88 xc->getCpuPtr()->wakeup(xc->threadId());
89 }
90}
91
92template <class XC>
93inline void
94handleLockedRead(XC *xc, Request *req)
95{
96 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
97 xc->setMiscReg(MISCREG_LOCKFLAG, true);
98 DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(),
99 req->getPaddr());
100}
101
102template <class XC>
103inline void
104handleLockedSnoopHit(XC *xc)
105{
106 DPRINTF(LLSC,"%s: handling snoop lock hit address: %#x\n",
107 xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR));
108 xc->setMiscReg(MISCREG_LOCKFLAG, false);
109 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
110}
111
112template <class XC>
113inline bool
114handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
115{
116 if (req->isSwap())
117 return true;
118
119 DPRINTF(LLSC,"%s: handling locked write for address %#x in monitor\n",
120 xc->getCpuPtr()->name(), req->getPaddr());
121 // Verify that the lock flag is still set and the address
122 // is correct
123 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
124 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
125 if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
126 // Lock flag not set or addr mismatch in CPU;
127 // don't even bother sending to memory system
128 req->setExtraData(0);
129 xc->setMiscReg(MISCREG_LOCKFLAG, false);
130 DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n",
131 xc->getCpuPtr()->name());
132 // the rest of this code is not architectural;
133 // it's just a debugging aid to help detect
134 // livelock by warning on long sequences of failed
135 // store conditionals
136 int stCondFailures = xc->readStCondFailures();
137 stCondFailures++;
138 xc->setStCondFailures(stCondFailures);
139 if (stCondFailures % 100000 == 0) {
140 warn("context %d: %d consecutive "
141 "store conditional failures\n",
142 xc->contextId(), stCondFailures);
143 }
144
145 // store conditional failed already, so don't issue it to mem
146 return false;
147 }
148 return true;
149}
150
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Steve Reinhardt
43 * Stephen Hines
44 */
45
46#ifndef __ARCH_ARM_LOCKED_MEM_HH__
47#define __ARCH_ARM_LOCKED_MEM_HH__
48
49/**
50 * @file
51 *
52 * ISA-specific helper functions for locked memory accesses.
53 */
54
55#include "arch/arm/miscregs.hh"
56#include "arch/arm/isa_traits.hh"
57#include "debug/LLSC.hh"
58#include "mem/packet.hh"
59#include "mem/request.hh"
60
61namespace ArmISA
62{
63template <class XC>
64inline void
65handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
66{
67 // Should only every see invalidations / direct writes
68 assert(pkt->isInvalidate() || pkt->isWrite());
69
70 DPRINTF(LLSC,"%s: handling snoop for address: %#x locked: %d\n",
71 xc->getCpuPtr()->name(),pkt->getAddr(),
72 xc->readMiscReg(MISCREG_LOCKFLAG));
73 if (!xc->readMiscReg(MISCREG_LOCKFLAG))
74 return;
75
76 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
77 // If no caches are attached, the snoop address always needs to be masked
78 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
79
80 DPRINTF(LLSC,"%s: handling snoop for address: %#x locked addr: %#x\n",
81 xc->getCpuPtr()->name(),snoop_addr, locked_addr);
82 if (locked_addr == snoop_addr) {
83 DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
84 xc->getCpuPtr()->name());
85 xc->setMiscReg(MISCREG_LOCKFLAG, false);
86 // Implement ARMv8 WFE/SEV semantics
87 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
88 xc->getCpuPtr()->wakeup(xc->threadId());
89 }
90}
91
92template <class XC>
93inline void
94handleLockedRead(XC *xc, Request *req)
95{
96 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
97 xc->setMiscReg(MISCREG_LOCKFLAG, true);
98 DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(),
99 req->getPaddr());
100}
101
102template <class XC>
103inline void
104handleLockedSnoopHit(XC *xc)
105{
106 DPRINTF(LLSC,"%s: handling snoop lock hit address: %#x\n",
107 xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR));
108 xc->setMiscReg(MISCREG_LOCKFLAG, false);
109 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
110}
111
112template <class XC>
113inline bool
114handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
115{
116 if (req->isSwap())
117 return true;
118
119 DPRINTF(LLSC,"%s: handling locked write for address %#x in monitor\n",
120 xc->getCpuPtr()->name(), req->getPaddr());
121 // Verify that the lock flag is still set and the address
122 // is correct
123 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
124 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
125 if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
126 // Lock flag not set or addr mismatch in CPU;
127 // don't even bother sending to memory system
128 req->setExtraData(0);
129 xc->setMiscReg(MISCREG_LOCKFLAG, false);
130 DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n",
131 xc->getCpuPtr()->name());
132 // the rest of this code is not architectural;
133 // it's just a debugging aid to help detect
134 // livelock by warning on long sequences of failed
135 // store conditionals
136 int stCondFailures = xc->readStCondFailures();
137 stCondFailures++;
138 xc->setStCondFailures(stCondFailures);
139 if (stCondFailures % 100000 == 0) {
140 warn("context %d: %d consecutive "
141 "store conditional failures\n",
142 xc->contextId(), stCondFailures);
143 }
144
145 // store conditional failed already, so don't issue it to mem
146 return false;
147 }
148 return true;
149}
150
|