1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 * Steve Reinhardt
31 * Stephen Hines
32 */
33
34#ifndef __ARCH_ARM_LOCKED_MEM_HH__
35#define __ARCH_ARM_LOCKED_MEM_HH__
36
37/**
38 * @file
39 *
40 * ISA-specific helper functions for locked memory accesses.
41 */
42
43#include "arch/arm/miscregs.hh"
44#include "mem/request.hh"
45
46namespace ArmISA
47{
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
52 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
53 xc->setMiscReg(MISCREG_LOCKFLAG, true);
54}
55
56
57template <class XC>
58inline bool
59handleLockedWrite(XC *xc, Request *req)
60{
61 if (req->isSwap())
62 return true;
63
64 // Verify that the lock flag is still set and the address
65 // is correct
66 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
67 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
68 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
69 // Lock flag not set or addr mismatch in CPU;
70 // don't even bother sending to memory system
71 req->setExtraData(0);
72 xc->setMiscReg(MISCREG_LOCKFLAG, false);
73 // the rest of this code is not architectural;
74 // it's just a debugging aid to help detect
75 // livelock by warning on long sequences of failed
76 // store conditionals
77 int stCondFailures = xc->readStCondFailures();
78 stCondFailures++;
79 xc->setStCondFailures(stCondFailures);
80 if (stCondFailures % 100000 == 0) {
81 warn("context %d: %d consecutive "
82 "store conditional failures\n",
83 xc->contextId(), stCondFailures);
84 }
85
86 // store conditional failed already, so don't issue it to mem
87 return false;
88 }
89 return true;
90}
91
92
93} // namespace ArmISA
94
95#endif