gic.hh (10905:a6ca6831e775) gic.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71 * @warn This GIC model cannot be used with simulated CPUs!
72 */
73class KvmGic : public BaseGic
74{
75 public: // SimObject / Serializable / Drainable
76 KvmGic(const KvmGicParams *p);
77 ~KvmGic();
78
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 62 unchanged lines hidden (view full) ---

71 * @warn This GIC model cannot be used with simulated CPUs!
72 */
73class KvmGic : public BaseGic
74{
75 public: // SimObject / Serializable / Drainable
76 KvmGic(const KvmGicParams *p);
77 ~KvmGic();
78
79 void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
80 void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
79 void startup() override { verifyMemoryMode(); }
80 void drainResume() override { verifyMemoryMode(); }
81
81
82 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
83 void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
82 void serialize(CheckpointOut &cp) const override;
83 void unserialize(Checkpoint *cp, const std::string &sec) override;
84
85 public: // PioDevice
86 AddrRangeList getAddrRanges() const { return addrRanges; }
84
85 public: // PioDevice
86 AddrRangeList getAddrRanges() const { return addrRanges; }
87 Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
88 Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
87 Tick read(PacketPtr pkt) override;
88 Tick write(PacketPtr pkt) override;
89
90 public: // BaseGic
89
90 public: // BaseGic
91 void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
92 void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
91 void sendInt(uint32_t num) override;
92 void clearInt(uint32_t num) override;
93
93
94 void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
95 void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
94 void sendPPInt(uint32_t num, uint32_t cpu) override;
95 void clearPPInt(uint32_t num, uint32_t cpu) override;
96
97 protected:
98 /**
99 * Do memory mode sanity checks
100 *
101 * This method only really exists to warn users that try to switch
102 * to a simulate CPU. There is no fool proof method to detect
103 * simulated CPUs, but checking that we're in atomic mode and

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97 protected:
98 /**
99 * Do memory mode sanity checks
100 *
101 * This method only really exists to warn users that try to switch
102 * to a simulate CPU. There is no fool proof method to detect
103 * simulated CPUs, but checking that we're in atomic mode and

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