1/*
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2 * Copyright (c) 2015-2016 ARM Limited
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2 * Copyright (c) 2015-2017 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg
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38 * Curtis Dunham |
39 */ 40 41#ifndef __ARCH_ARM_KVM_GIC_HH__ 42#define __ARCH_ARM_KVM_GIC_HH__ 43 44#include "arch/arm/system.hh" 45#include "cpu/kvm/device.hh" 46#include "cpu/kvm/vm.hh" 47#include "dev/arm/base_gic.hh"
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48#include "dev/arm/gic_pl390.hh" |
49#include "dev/platform.hh" 50 51/** 52 * KVM in-kernel GIC abstraction 53 * 54 * This class defines a high-level interface to the KVM in-kernel GIC 55 * model. It exposes an API that is similar to that of 56 * software-emulated GIC models in gem5. 57 */ 58class KvmKernelGicV2 59{ 60 public: 61 /** 62 * Instantiate a KVM in-kernel GIC model. 63 * 64 * This constructor instantiates an in-kernel GIC model and wires 65 * it up to the virtual memory system. 66 * 67 * @param vm KVM VM representing this system 68 * @param cpu_addr GIC CPU interface base address 69 * @param dist_addr GIC distributor base address 70 * @param it_lines Number of interrupt lines to support 71 */ 72 KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr, 73 unsigned it_lines); 74 virtual ~KvmKernelGicV2(); 75 76 KvmKernelGicV2(const KvmKernelGicV2 &other) = delete; 77 KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete; 78 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete; 79 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete; 80 81 public: 82 /** 83 * @{ 84 * @name In-kernel GIC API 85 */ 86 87 /** 88 * Raise a shared peripheral interrupt 89 * 90 * @param spi SPI number 91 */ 92 void setSPI(unsigned spi); 93 /** 94 * Clear a shared peripheral interrupt 95 * 96 * @param spi SPI number 97 */ 98 void clearSPI(unsigned spi); 99 100 /** 101 * Raise a private peripheral interrupt 102 * 103 * @param vcpu KVM virtual CPU number 104 * @parma ppi PPI interrupt number 105 */ 106 void setPPI(unsigned vcpu, unsigned ppi); 107 108 /** 109 * Clear a private peripheral interrupt 110 * 111 * @param vcpu KVM virtual CPU number 112 * @parma ppi PPI interrupt number 113 */ 114 void clearPPI(unsigned vcpu, unsigned ppi); 115 116 /** Address range for the CPU interfaces */ 117 const AddrRange cpuRange; 118 /** Address range for the distributor interface */ 119 const AddrRange distRange; 120 121 /* @} */ 122 123 protected: 124 /** 125 * Update the kernel's VGIC interrupt state 126 * 127 * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI) 128 * @param vcpu CPU id within KVM (ignored for SPIs) 129 * @param irq Interrupt number 130 * @param high True to signal an interrupt, false to clear it. 131 */ 132 void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high); 133 134 /** KVM VM in the parent system */ 135 KvmVM &vm; 136 137 /** Kernel interface to the GIC */ 138 KvmDevice kdev; 139}; 140 141struct KvmGicParams; 142 143/** 144 * In-kernel GIC model. 145 * 146 * When using a KVM-based CPU model, it is possible to offload GIC 147 * emulation to the kernel. This reduces some overheads when the guest 148 * accesses the GIC and makes it possible to use in-kernel 149 * architected/generic timer emulation. 150 * 151 * This device uses interfaces with the kernel GicV2 model that is 152 * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the 153 * Linux kernel sources. 154 * 155 * This GIC model has the following known limitations: 156 * <ul> 157 * <li>Checkpointing is not supported. 158 * <li>This model only works with kvm. Simulated CPUs are not 159 * supported since this would require the kernel to inject 160 * interrupt into the simulated CPU. 161 * </ul> 162 * 163 * @warn This GIC model cannot be used with simulated CPUs! 164 */ 165class KvmGic : public BaseGic 166{ 167 public: // SimObject / Serializable / Drainable 168 KvmGic(const KvmGicParams *p); 169 ~KvmGic(); 170 171 void startup() override { verifyMemoryMode(); } 172 void drainResume() override { verifyMemoryMode(); } 173 174 void serialize(CheckpointOut &cp) const override; 175 void unserialize(CheckpointIn &cp) override; 176 177 public: // PioDevice 178 AddrRangeList getAddrRanges() const { return addrRanges; } 179 Tick read(PacketPtr pkt) override; 180 Tick write(PacketPtr pkt) override; 181 182 public: // BaseGic 183 void sendInt(uint32_t num) override; 184 void clearInt(uint32_t num) override; 185 186 void sendPPInt(uint32_t num, uint32_t cpu) override; 187 void clearPPInt(uint32_t num, uint32_t cpu) override; 188 189 protected: 190 /** 191 * Do memory mode sanity checks 192 * 193 * This method only really exists to warn users that try to switch 194 * to a simulate CPU. There is no fool proof method to detect 195 * simulated CPUs, but checking that we're in atomic mode and 196 * bypassing caches should be robust enough. 197 */ 198 void verifyMemoryMode() const; 199 200 /** System this interrupt controller belongs to */ 201 System &system; 202 203 /** Kernel GIC device */ 204 KvmKernelGicV2 kernelGic; 205 206 /** Union of all memory */ 207 const AddrRangeList addrRanges; 208}; 209
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210struct MuxingKvmGicParams; 211 212class MuxingKvmGic : public Pl390 213{ 214 public: // SimObject / Serializable / Drainable 215 MuxingKvmGic(const MuxingKvmGicParams *p); 216 ~MuxingKvmGic(); 217 218 void startup() override; 219 void drainResume() override; 220 221 void serialize(CheckpointOut &cp) const override; 222 void unserialize(CheckpointIn &cp) override; 223 224 public: // PioDevice 225 Tick read(PacketPtr pkt) override; 226 Tick write(PacketPtr pkt) override; 227 228 public: // Pl390 229 void sendInt(uint32_t num) override; 230 void clearInt(uint32_t num) override; 231 232 void sendPPInt(uint32_t num, uint32_t cpu) override; 233 void clearPPInt(uint32_t num, uint32_t cpu) override; 234 235 protected: 236 /** Verify gem5 configuration will support KVM emulation */ 237 bool validKvmEnvironment() const; 238 239 /** System this interrupt controller belongs to */ 240 System &system; 241 242 /** Kernel GIC device */ 243 KvmKernelGicV2 *kernelGic; 244 245 private: 246 bool usingKvm; 247 248 /** Multiplexing implementation: state transfer functions */ 249 void fromPl390ToKvm(); 250 void fromKvmToPl390(); 251}; 252 |
253#endif // __ARCH_ARM_KVM_GIC_HH__
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