1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_KVM_GIC_HH__
41#define __ARCH_ARM_KVM_GIC_HH__
42
43#include "arch/arm/system.hh"
44#include "cpu/kvm/device.hh"
45#include "cpu/kvm/vm.hh"
46#include "dev/arm/base_gic.hh"
47#include "dev/platform.hh"
48
49/**
50 * KVM in-kernel GIC abstraction
51 *
52 * This class defines a high-level interface to the KVM in-kernel GIC
53 * model. It exposes an API that is similar to that of
54 * software-emulated GIC models in gem5.
55 */
56class KvmKernelGicV2
57{
58 public:
59 /**
60 * Instantiate a KVM in-kernel GIC model.
61 *
62 * This constructor instantiates an in-kernel GIC model and wires
63 * it up to the virtual memory system.
64 *
65 * @param vm KVM VM representing this system
66 * @param cpu_addr GIC CPU interface base address
67 * @param dist_addr GIC distributor base address
| 1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_KVM_GIC_HH__
41#define __ARCH_ARM_KVM_GIC_HH__
42
43#include "arch/arm/system.hh"
44#include "cpu/kvm/device.hh"
45#include "cpu/kvm/vm.hh"
46#include "dev/arm/base_gic.hh"
47#include "dev/platform.hh"
48
49/**
50 * KVM in-kernel GIC abstraction
51 *
52 * This class defines a high-level interface to the KVM in-kernel GIC
53 * model. It exposes an API that is similar to that of
54 * software-emulated GIC models in gem5.
55 */
56class KvmKernelGicV2
57{
58 public:
59 /**
60 * Instantiate a KVM in-kernel GIC model.
61 *
62 * This constructor instantiates an in-kernel GIC model and wires
63 * it up to the virtual memory system.
64 *
65 * @param vm KVM VM representing this system
66 * @param cpu_addr GIC CPU interface base address
67 * @param dist_addr GIC distributor base address
|
69 */
70 KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr,
71 unsigned it_lines);
72 virtual ~KvmKernelGicV2();
73
74 KvmKernelGicV2(const KvmKernelGicV2 &other) = delete;
75 KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete;
76 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete;
77 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete;
78
79 public:
80 /**
81 * @{
82 * @name In-kernel GIC API
83 */
84
85 /**
86 * Raise a shared peripheral interrupt
87 *
88 * @param spi SPI number
89 */
90 void setSPI(unsigned spi);
91 /**
92 * Clear a shared peripheral interrupt
93 *
94 * @param spi SPI number
95 */
96 void clearSPI(unsigned spi);
97
98 /**
99 * Raise a private peripheral interrupt
100 *
101 * @param vcpu KVM virtual CPU number
102 * @parma ppi PPI interrupt number
103 */
104 void setPPI(unsigned vcpu, unsigned ppi);
105
106 /**
107 * Clear a private peripheral interrupt
108 *
109 * @param vcpu KVM virtual CPU number
110 * @parma ppi PPI interrupt number
111 */
112 void clearPPI(unsigned vcpu, unsigned ppi);
113
114 /** Address range for the CPU interfaces */
115 const AddrRange cpuRange;
116 /** Address range for the distributor interface */
117 const AddrRange distRange;
118
119 /* @} */
120
121 protected:
122 /**
123 * Update the kernel's VGIC interrupt state
124 *
125 * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI)
126 * @param vcpu CPU id within KVM (ignored for SPIs)
127 * @param irq Interrupt number
128 * @param high True to signal an interrupt, false to clear it.
129 */
130 void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
131
132 /** KVM VM in the parent system */
133 KvmVM &vm;
134
135 /** Kernel interface to the GIC */
136 KvmDevice kdev;
137};
138
139struct KvmGicParams;
140
141/**
142 * In-kernel GIC model.
143 *
144 * When using a KVM-based CPU model, it is possible to offload GIC
145 * emulation to the kernel. This reduces some overheads when the guest
146 * accesses the GIC and makes it possible to use in-kernel
147 * architected/generic timer emulation.
148 *
149 * This device uses interfaces with the kernel GicV2 model that is
150 * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
151 * Linux kernel sources.
152 *
153 * This GIC model has the following known limitations:
154 * <ul>
155 * <li>Checkpointing is not supported.
156 * <li>This model only works with kvm. Simulated CPUs are not
157 * supported since this would require the kernel to inject
158 * interrupt into the simulated CPU.
159 * </ul>
160 *
161 * @warn This GIC model cannot be used with simulated CPUs!
162 */
163class KvmGic : public BaseGic
164{
165 public: // SimObject / Serializable / Drainable
166 KvmGic(const KvmGicParams *p);
167 ~KvmGic();
168
169 void startup() override { verifyMemoryMode(); }
170 void drainResume() override { verifyMemoryMode(); }
171
172 void serialize(CheckpointOut &cp) const override;
173 void unserialize(CheckpointIn &cp) override;
174
175 public: // PioDevice
176 AddrRangeList getAddrRanges() const { return addrRanges; }
177 Tick read(PacketPtr pkt) override;
178 Tick write(PacketPtr pkt) override;
179
180 public: // BaseGic
181 void sendInt(uint32_t num) override;
182 void clearInt(uint32_t num) override;
183
184 void sendPPInt(uint32_t num, uint32_t cpu) override;
185 void clearPPInt(uint32_t num, uint32_t cpu) override;
186
187 protected:
188 /**
189 * Do memory mode sanity checks
190 *
191 * This method only really exists to warn users that try to switch
192 * to a simulate CPU. There is no fool proof method to detect
193 * simulated CPUs, but checking that we're in atomic mode and
194 * bypassing caches should be robust enough.
195 */
196 void verifyMemoryMode() const;
197
198 /** System this interrupt controller belongs to */
199 System &system;
200
201 /** Kernel GIC device */
202 KvmKernelGicV2 kernelGic;
203
204 /** Union of all memory */
205 const AddrRangeList addrRanges;
206};
207
208#endif // __ARCH_ARM_KVM_GIC_HH__
| 69 */
70 KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr,
71 unsigned it_lines);
72 virtual ~KvmKernelGicV2();
73
74 KvmKernelGicV2(const KvmKernelGicV2 &other) = delete;
75 KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete;
76 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete;
77 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete;
78
79 public:
80 /**
81 * @{
82 * @name In-kernel GIC API
83 */
84
85 /**
86 * Raise a shared peripheral interrupt
87 *
88 * @param spi SPI number
89 */
90 void setSPI(unsigned spi);
91 /**
92 * Clear a shared peripheral interrupt
93 *
94 * @param spi SPI number
95 */
96 void clearSPI(unsigned spi);
97
98 /**
99 * Raise a private peripheral interrupt
100 *
101 * @param vcpu KVM virtual CPU number
102 * @parma ppi PPI interrupt number
103 */
104 void setPPI(unsigned vcpu, unsigned ppi);
105
106 /**
107 * Clear a private peripheral interrupt
108 *
109 * @param vcpu KVM virtual CPU number
110 * @parma ppi PPI interrupt number
111 */
112 void clearPPI(unsigned vcpu, unsigned ppi);
113
114 /** Address range for the CPU interfaces */
115 const AddrRange cpuRange;
116 /** Address range for the distributor interface */
117 const AddrRange distRange;
118
119 /* @} */
120
121 protected:
122 /**
123 * Update the kernel's VGIC interrupt state
124 *
125 * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI)
126 * @param vcpu CPU id within KVM (ignored for SPIs)
127 * @param irq Interrupt number
128 * @param high True to signal an interrupt, false to clear it.
129 */
130 void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
131
132 /** KVM VM in the parent system */
133 KvmVM &vm;
134
135 /** Kernel interface to the GIC */
136 KvmDevice kdev;
137};
138
139struct KvmGicParams;
140
141/**
142 * In-kernel GIC model.
143 *
144 * When using a KVM-based CPU model, it is possible to offload GIC
145 * emulation to the kernel. This reduces some overheads when the guest
146 * accesses the GIC and makes it possible to use in-kernel
147 * architected/generic timer emulation.
148 *
149 * This device uses interfaces with the kernel GicV2 model that is
150 * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
151 * Linux kernel sources.
152 *
153 * This GIC model has the following known limitations:
154 * <ul>
155 * <li>Checkpointing is not supported.
156 * <li>This model only works with kvm. Simulated CPUs are not
157 * supported since this would require the kernel to inject
158 * interrupt into the simulated CPU.
159 * </ul>
160 *
161 * @warn This GIC model cannot be used with simulated CPUs!
162 */
163class KvmGic : public BaseGic
164{
165 public: // SimObject / Serializable / Drainable
166 KvmGic(const KvmGicParams *p);
167 ~KvmGic();
168
169 void startup() override { verifyMemoryMode(); }
170 void drainResume() override { verifyMemoryMode(); }
171
172 void serialize(CheckpointOut &cp) const override;
173 void unserialize(CheckpointIn &cp) override;
174
175 public: // PioDevice
176 AddrRangeList getAddrRanges() const { return addrRanges; }
177 Tick read(PacketPtr pkt) override;
178 Tick write(PacketPtr pkt) override;
179
180 public: // BaseGic
181 void sendInt(uint32_t num) override;
182 void clearInt(uint32_t num) override;
183
184 void sendPPInt(uint32_t num, uint32_t cpu) override;
185 void clearPPInt(uint32_t num, uint32_t cpu) override;
186
187 protected:
188 /**
189 * Do memory mode sanity checks
190 *
191 * This method only really exists to warn users that try to switch
192 * to a simulate CPU. There is no fool proof method to detect
193 * simulated CPUs, but checking that we're in atomic mode and
194 * bypassing caches should be robust enough.
195 */
196 void verifyMemoryMode() const;
197
198 /** System this interrupt controller belongs to */
199 System &system;
200
201 /** Kernel GIC device */
202 KvmKernelGicV2 kernelGic;
203
204 /** Union of all memory */
205 const AddrRangeList addrRanges;
206};
207
208#endif // __ARCH_ARM_KVM_GIC_HH__
|