gic.cc (12515:e3d1a64d0260) gic.cc (13014:a4f71c3dc602)
1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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163{
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166}
167
168
169
170MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 154 unchanged lines hidden (view full) ---

163{
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166}
167
168
169
170MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
171 : Pl390(p),
171 : GicV2(p),
172 system(*p->system),
173 kernelGic(nullptr),
174 usingKvm(false)
175{
176 if (auto vm = system.getKvmVM()) {
177 kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
178 p->it_lines);
179 }
180}
181
182MuxingKvmGic::~MuxingKvmGic()
183{
184}
185
186void
187MuxingKvmGic::startup()
188{
172 system(*p->system),
173 kernelGic(nullptr),
174 usingKvm(false)
175{
176 if (auto vm = system.getKvmVM()) {
177 kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
178 p->it_lines);
179 }
180}
181
182MuxingKvmGic::~MuxingKvmGic()
183{
184}
185
186void
187MuxingKvmGic::startup()
188{
189 Pl390::startup();
189 GicV2::startup();
190 usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
191 if (usingKvm)
190 usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
191 if (usingKvm)
192 fromPl390ToKvm();
192 fromGicV2ToKvm();
193}
194
195DrainState
196MuxingKvmGic::drain()
197{
198 if (usingKvm)
193}
194
195DrainState
196MuxingKvmGic::drain()
197{
198 if (usingKvm)
199 fromKvmToPl390();
200 return Pl390::drain();
199 fromKvmToGicV2();
200 return GicV2::drain();
201}
202
203void
204MuxingKvmGic::drainResume()
205{
201}
202
203void
204MuxingKvmGic::drainResume()
205{
206 Pl390::drainResume();
206 GicV2::drainResume();
207 bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
208 if (use_kvm != usingKvm) {
209 // Should only occur due to CPU switches
210 if (use_kvm) // from simulation to KVM emulation
207 bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
208 if (use_kvm != usingKvm) {
209 // Should only occur due to CPU switches
210 if (use_kvm) // from simulation to KVM emulation
211 fromPl390ToKvm();
212 // otherwise, drain() already sync'd the state back to the Pl390
211 fromGicV2ToKvm();
212 // otherwise, drain() already sync'd the state back to the GicV2
213
214 usingKvm = use_kvm;
215 }
216}
217
218Tick
219MuxingKvmGic::read(PacketPtr pkt)
220{
221 if (!usingKvm)
213
214 usingKvm = use_kvm;
215 }
216}
217
218Tick
219MuxingKvmGic::read(PacketPtr pkt)
220{
221 if (!usingKvm)
222 return Pl390::read(pkt);
222 return GicV2::read(pkt);
223
224 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
225}
226
227Tick
228MuxingKvmGic::write(PacketPtr pkt)
229{
230 if (!usingKvm)
223
224 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
225}
226
227Tick
228MuxingKvmGic::write(PacketPtr pkt)
229{
230 if (!usingKvm)
231 return Pl390::write(pkt);
231 return GicV2::write(pkt);
232
233 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
234}
235
236void
237MuxingKvmGic::sendInt(uint32_t num)
238{
239 if (!usingKvm)
232
233 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
234}
235
236void
237MuxingKvmGic::sendInt(uint32_t num)
238{
239 if (!usingKvm)
240 return Pl390::sendInt(num);
240 return GicV2::sendInt(num);
241
242 DPRINTF(Interrupt, "Set SPI %d\n", num);
243 kernelGic->setSPI(num);
244}
245
246void
247MuxingKvmGic::clearInt(uint32_t num)
248{
249 if (!usingKvm)
241
242 DPRINTF(Interrupt, "Set SPI %d\n", num);
243 kernelGic->setSPI(num);
244}
245
246void
247MuxingKvmGic::clearInt(uint32_t num)
248{
249 if (!usingKvm)
250 return Pl390::clearInt(num);
250 return GicV2::clearInt(num);
251
252 DPRINTF(Interrupt, "Clear SPI %d\n", num);
253 kernelGic->clearSPI(num);
254}
255
256void
257MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
258{
259 if (!usingKvm)
251
252 DPRINTF(Interrupt, "Clear SPI %d\n", num);
253 kernelGic->clearSPI(num);
254}
255
256void
257MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
258{
259 if (!usingKvm)
260 return Pl390::sendPPInt(num, cpu);
260 return GicV2::sendPPInt(num, cpu);
261 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
262 kernelGic->setPPI(cpu, num);
263}
264
265void
266MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
267{
268 if (!usingKvm)
261 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
262 kernelGic->setPPI(cpu, num);
263}
264
265void
266MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
267{
268 if (!usingKvm)
269 return Pl390::clearPPInt(num, cpu);
269 return GicV2::clearPPInt(num, cpu);
270
271 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
272 kernelGic->clearPPI(cpu, num);
273}
274
275void
276MuxingKvmGic::updateIntState(int hint)
277{
270
271 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
272 kernelGic->clearPPI(cpu, num);
273}
274
275void
276MuxingKvmGic::updateIntState(int hint)
277{
278 // During Kvm->Pl390 state transfer, writes to the Pl390 will call
278 // During Kvm->GicV2 state transfer, writes to the GicV2 will call
279 // updateIntState() which can post an interrupt. Since we're only
279 // updateIntState() which can post an interrupt. Since we're only
280 // using the Pl390 model for holding state in this circumstance, we
281 // short-circuit this behavior, as the Pl390 is not actually active.
280 // using the GicV2 model for holding state in this circumstance, we
281 // short-circuit this behavior, as the GicV2 is not actually active.
282 if (!usingKvm)
282 if (!usingKvm)
283 return Pl390::updateIntState(hint);
283 return GicV2::updateIntState(hint);
284}
285
286void
287MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
288 ContextID ctx, Addr daddr)
289{
290 auto val = from->readDistributor(ctx, daddr);
291 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);

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352 }
353
354
355 /// Distributor state (GICD_*)
356 // Copy Distributor Control Register (CTLR)
357 copyDistRegister(from, to, 0, GICD_CTLR);
358
359 // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
284}
285
286void
287MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
288 ContextID ctx, Addr daddr)
289{
290 auto val = from->readDistributor(ctx, daddr);
291 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);

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352 }
353
354
355 /// Distributor state (GICD_*)
356 // Copy Distributor Control Register (CTLR)
357 copyDistRegister(from, to, 0, GICD_CTLR);
358
359 // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
360 set = Pl390::GICD_ISENABLER.start();
361 clear = Pl390::GICD_ICENABLER.start();
362 size = Pl390::itLines / 8;
360 set = GicV2::GICD_ISENABLER.start();
361 clear = GicV2::GICD_ICENABLER.start();
362 size = GicV2::itLines / 8;
363 clearBankedDistRange(to, clear, 4);
364 copyBankedDistRange(from, to, set, 4);
365
366 set += 4, clear += 4, size -= 4;
367 clearDistRange(to, clear, size);
368 copyDistRange(from, to, set, size);
369
370 // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
363 clearBankedDistRange(to, clear, 4);
364 copyBankedDistRange(from, to, set, 4);
365
366 set += 4, clear += 4, size -= 4;
367 clearDistRange(to, clear, size);
368 copyDistRange(from, to, set, size);
369
370 // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
371 set = Pl390::GICD_ISPENDR.start();
372 clear = Pl390::GICD_ICPENDR.start();
373 size = Pl390::itLines / 8;
371 set = GicV2::GICD_ISPENDR.start();
372 clear = GicV2::GICD_ICPENDR.start();
373 size = GicV2::itLines / 8;
374 clearBankedDistRange(to, clear, 4);
375 copyBankedDistRange(from, to, set, 4);
376
377 set += 4, clear += 4, size -= 4;
378 clearDistRange(to, clear, size);
379 copyDistRange(from, to, set, size);
380
381 // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
374 clearBankedDistRange(to, clear, 4);
375 copyBankedDistRange(from, to, set, 4);
376
377 set += 4, clear += 4, size -= 4;
378 clearDistRange(to, clear, size);
379 copyDistRange(from, to, set, size);
380
381 // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
382 set = Pl390::GICD_ISACTIVER.start();
383 clear = Pl390::GICD_ICACTIVER.start();
384 size = Pl390::itLines / 8;
382 set = GicV2::GICD_ISACTIVER.start();
383 clear = GicV2::GICD_ICACTIVER.start();
384 size = GicV2::itLines / 8;
385 clearBankedDistRange(to, clear, 4);
386 copyBankedDistRange(from, to, set, 4);
387
388 set += 4, clear += 4, size -= 4;
389 clearDistRange(to, clear, size);
390 copyDistRange(from, to, set, size);
391
392 // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
385 clearBankedDistRange(to, clear, 4);
386 copyBankedDistRange(from, to, set, 4);
387
388 set += 4, clear += 4, size -= 4;
389 clearDistRange(to, clear, size);
390 copyDistRange(from, to, set, size);
391
392 // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
393 set = Pl390::GICD_IPRIORITYR.start();
393 set = GicV2::GICD_IPRIORITYR.start();
394 copyBankedDistRange(from, to, set, 32);
395
396 set += 32;
394 copyBankedDistRange(from, to, set, 32);
395
396 set += 32;
397 size = Pl390::itLines - 32;
397 size = GicV2::itLines - 32;
398 copyDistRange(from, to, set, size);
399
400 // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
398 copyDistRange(from, to, set, size);
399
400 // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
401 set = Pl390::GICD_ITARGETSR.start() + 32;
402 size = Pl390::itLines - 32;
401 set = GicV2::GICD_ITARGETSR.start() + 32;
402 size = GicV2::itLines - 32;
403 copyDistRange(from, to, set, size);
404
405 // Copy interrupt configuration registers (ICFGRn)
403 copyDistRange(from, to, set, size);
404
405 // Copy interrupt configuration registers (ICFGRn)
406 set = Pl390::GICD_ICFGR.start();
407 size = Pl390::itLines / 4;
406 set = GicV2::GICD_ICFGR.start();
407 size = GicV2::itLines / 4;
408 copyDistRange(from, to, set, size);
409}
410
411void
408 copyDistRange(from, to, set, size);
409}
410
411void
412MuxingKvmGic::fromPl390ToKvm()
412MuxingKvmGic::fromGicV2ToKvm()
413{
413{
414 copyGicState(static_cast<Pl390*>(this), kernelGic);
414 copyGicState(static_cast<GicV2*>(this), kernelGic);
415}
416
417void
415}
416
417void
418MuxingKvmGic::fromKvmToPl390()
418MuxingKvmGic::fromKvmToGicV2()
419{
419{
420 copyGicState(kernelGic, static_cast<Pl390*>(this));
420 copyGicState(kernelGic, static_cast<GicV2*>(this));
421
422 // the values read for the Interrupt Priority Mask Register (PMR)
423 // have been shifted by three bits due to its having been emulated by
424 // a VGIC with only 5 PMR bits in its VMCR register. Presently the
425 // Linux kernel does not repair this inaccuracy, so we correct it here.
426 for (int cpu = 0; cpu < system.numContexts(); ++cpu) {
427 cpuPriority[cpu] <<= 3;
428 assert((cpuPriority[cpu] & ~0xff) == 0);
429 }
430}
431
432MuxingKvmGic *
433MuxingKvmGicParams::create()
434{
435 return new MuxingKvmGic(this);
436}
421
422 // the values read for the Interrupt Priority Mask Register (PMR)
423 // have been shifted by three bits due to its having been emulated by
424 // a VGIC with only 5 PMR bits in its VMCR register. Presently the
425 // Linux kernel does not repair this inaccuracy, so we correct it here.
426 for (int cpu = 0; cpu < system.numContexts(); ++cpu) {
427 cpuPriority[cpu] <<= 3;
428 assert((cpuPriority[cpu] & ~0xff) == 0);
429 }
430}
431
432MuxingKvmGic *
433MuxingKvmGicParams::create()
434{
435 return new MuxingKvmGic(this);
436}