1/*
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2 * Copyright (c) 2015 ARM Limited
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2 * Copyright (c) 2015-2016 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 */ 39 40#include "arch/arm/kvm/gic.hh" 41 42#include <linux/kvm.h> 43 44#include "debug/Interrupt.hh" 45#include "params/KvmGic.hh" 46
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47 48KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr) 49 : cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)), 50 distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)), 51 vm(_vm), 52 kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2)) 53{ 54 kdev.setAttr<uint64_t>( 55 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr); 56 kdev.setAttr<uint64_t>( 57 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr); 58} 59 60KvmKernelGicV2::~KvmKernelGicV2() 61{ 62} 63 64void 65KvmKernelGicV2::setSPI(unsigned spi) 66{ 67 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true); 68} 69 70void 71KvmKernelGicV2::clearSPI(unsigned spi) 72{ 73 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false); 74} 75 76void 77KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi) 78{ 79 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true); 80} 81 82void 83KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi) 84{ 85 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false); 86} 87 88void 89KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq, 90 bool high) 91{ 92 assert(type <= KVM_ARM_IRQ_TYPE_MASK); 93 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK); 94 assert(irq <= KVM_ARM_IRQ_NUM_MASK); 95 const uint32_t line( 96 (type << KVM_ARM_IRQ_TYPE_SHIFT) | 97 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) | 98 (irq << KVM_ARM_IRQ_NUM_SHIFT)); 99 100 vm.setIRQLine(line, high); 101} 102 103 |
104KvmGic::KvmGic(const KvmGicParams *p) 105 : BaseGic(p), 106 system(*p->system),
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50 vm(*p->kvmVM),
51 kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2)),
52 distRange(RangeSize(p->dist_addr, KVM_VGIC_V2_DIST_SIZE)),
53 cpuRange(RangeSize(p->cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
54 addrRanges{distRange, cpuRange}
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107 kernelGic(*p->kvmVM, p->cpu_addr, p->dist_addr), 108 addrRanges{kernelGic.distRange, kernelGic.cpuRange} |
109{
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56 kdev.setAttr<uint64_t>(
57 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST,
58 p->dist_addr);
59 kdev.setAttr<uint64_t>(
60 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU,
61 p->cpu_addr);
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110} 111 112KvmGic::~KvmGic() 113{ 114} 115 116void 117KvmGic::serialize(CheckpointOut &cp) const 118{ 119 panic("Checkpointing unsupported\n"); 120} 121 122void 123KvmGic::unserialize(CheckpointIn &cp) 124{ 125 panic("Checkpointing unsupported\n"); 126} 127 128Tick 129KvmGic::read(PacketPtr pkt) 130{ 131 panic("KvmGic: PIO from gem5 is currently unsupported\n"); 132} 133 134Tick 135KvmGic::write(PacketPtr pkt) 136{ 137 panic("KvmGic: PIO from gem5 is currently unsupported\n"); 138} 139 140void 141KvmGic::sendInt(uint32_t num) 142{ 143 DPRINTF(Interrupt, "Set SPI %d\n", num);
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96 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, true);
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144 kernelGic.setSPI(num); |
145} 146 147void 148KvmGic::clearInt(uint32_t num) 149{ 150 DPRINTF(Interrupt, "Clear SPI %d\n", num);
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103 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, false);
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151 kernelGic.clearSPI(num); |
152} 153 154void 155KvmGic::sendPPInt(uint32_t num, uint32_t cpu) 156{ 157 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
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110 setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, true);
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158 kernelGic.setPPI(cpu, num); |
159} 160 161void 162KvmGic::clearPPInt(uint32_t num, uint32_t cpu) 163{ 164 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
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117 setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, false);
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165 kernelGic.clearPPI(cpu, num); |
166} 167 168void 169KvmGic::verifyMemoryMode() const 170{ 171 if (!(system.isAtomicMode() && system.bypassCaches())) { 172 fatal("The in-kernel KVM GIC can only be used with KVM CPUs, but the " 173 "current memory mode does not support KVM.\n"); 174 } 175} 176
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129void
130KvmGic::setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high)
131{
132 assert(type < KVM_ARM_IRQ_TYPE_MASK);
133 assert(vcpu < KVM_ARM_IRQ_VCPU_MASK);
134 assert(irq < KVM_ARM_IRQ_NUM_MASK);
135 const uint32_t line(
136 (type << KVM_ARM_IRQ_TYPE_SHIFT) |
137 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
138 (irq << KVM_ARM_IRQ_NUM_SHIFT));
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177
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140 vm.setIRQLine(line, high);
141}
142
143
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178KvmGic * 179KvmGicParams::create() 180{ 181 return new KvmGic(this); 182}
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