1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 * Curtis Dunham
39 */
40
41#include "arch/arm/kvm/gic.hh"
42
43#include <linux/kvm.h>
44
45#include "arch/arm/kvm/base_cpu.hh"
46#include "debug/GIC.hh"
47#include "debug/Interrupt.hh"
48#include "params/MuxingKvmGic.hh"
49
50KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
51 unsigned it_lines)
52 : cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
53 distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)),
54 vm(_vm),
55 kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
56{
57 // Tell the VM that we will emulate the GIC in the kernel. This
58 // disables IRQ and FIQ handling in the KVM CPU model.
59 vm.enableKernelIRQChip();
60
61 kdev.setAttr<uint64_t>(
62 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
63 kdev.setAttr<uint64_t>(
64 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
65
66 kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
67}
68
69KvmKernelGicV2::~KvmKernelGicV2()
70{
71}
72
73void
74KvmKernelGicV2::setSPI(unsigned spi)
75{
76 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
77}
78
79void
80KvmKernelGicV2::clearSPI(unsigned spi)
81{
82 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
83}
84
85void
86KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
87{
88 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
89}
90
91void
92KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
93{
94 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
95}
96
97void
98KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
99 bool high)
100{
101 assert(type <= KVM_ARM_IRQ_TYPE_MASK);
102 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
103 assert(irq <= KVM_ARM_IRQ_NUM_MASK);
104 const uint32_t line(
105 (type << KVM_ARM_IRQ_TYPE_SHIFT) |
106 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
107 (irq << KVM_ARM_IRQ_NUM_SHIFT));
108
109 vm.setIRQLine(line, high);
110}
111
112uint32_t
113KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
114{
115 uint64_t reg;
116
117 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
118 const uint32_t attr(
119 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
120 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
121
122 kdev.getAttrPtr(group, attr, ®);
123 return (uint32_t) reg;
124}
125
126void
127KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
128 unsigned value)
129{
130 uint64_t reg = value;
131
132 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
133 const uint32_t attr(
134 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
135 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
136
137 kdev.setAttrPtr(group, attr, ®);
138}
139
140uint32_t
141KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
142{
143 auto vcpu = vm.contextIdToVCpuId(ctx);
144 return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
145}
146
147uint32_t
148KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
149{
150 auto vcpu = vm.contextIdToVCpuId(ctx);
151 return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
152}
153
154void
155KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
156{
157 auto vcpu = vm.contextIdToVCpuId(ctx);
158 setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
159}
160
161void
162KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
163{
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166}
167
168
169
170MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
171 : Pl390(p),
172 system(*p->system),
173 kernelGic(nullptr),
174 usingKvm(false)
175{
176 if (auto vm = system.getKvmVM()) {
177 kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
178 p->it_lines);
179 }
180}
181
182MuxingKvmGic::~MuxingKvmGic()
183{
184}
185
186void
187MuxingKvmGic::startup()
188{
189 Pl390::startup();
190 usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
191 if (usingKvm)
192 fromPl390ToKvm();
193}
194
195DrainState
196MuxingKvmGic::drain()
197{
198 if (usingKvm)
199 fromKvmToPl390();
200 return Pl390::drain();
201}
202
203void
204MuxingKvmGic::drainResume()
205{
206 Pl390::drainResume();
207 bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
208 if (use_kvm != usingKvm) {
209 // Should only occur due to CPU switches
210 if (use_kvm) // from simulation to KVM emulation
211 fromPl390ToKvm();
212 // otherwise, drain() already sync'd the state back to the Pl390
213
214 usingKvm = use_kvm;
215 }
216}
217
218Tick
219MuxingKvmGic::read(PacketPtr pkt)
220{
221 if (!usingKvm)
222 return Pl390::read(pkt);
223
224 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
225}
226
227Tick
228MuxingKvmGic::write(PacketPtr pkt)
229{
230 if (!usingKvm)
231 return Pl390::write(pkt);
232
233 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
234}
235
236void
237MuxingKvmGic::sendInt(uint32_t num)
238{
239 if (!usingKvm)
240 return Pl390::sendInt(num);
241
242 DPRINTF(Interrupt, "Set SPI %d\n", num);
243 kernelGic->setSPI(num);
244}
245
246void
247MuxingKvmGic::clearInt(uint32_t num)
248{
249 if (!usingKvm)
250 return Pl390::clearInt(num);
251
252 DPRINTF(Interrupt, "Clear SPI %d\n", num);
253 kernelGic->clearSPI(num);
254}
255
256void
257MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
258{
259 if (!usingKvm)
260 return Pl390::sendPPInt(num, cpu);
261 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
262 kernelGic->setPPI(cpu, num);
263}
264
265void
266MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
267{
268 if (!usingKvm)
269 return Pl390::clearPPInt(num, cpu);
270
271 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
272 kernelGic->clearPPI(cpu, num);
273}
274
275void
276MuxingKvmGic::updateIntState(int hint)
277{
278 // During Kvm->Pl390 state transfer, writes to the Pl390 will call
279 // updateIntState() which can post an interrupt. Since we're only
280 // using the Pl390 model for holding state in this circumstance, we
281 // short-circuit this behavior, as the Pl390 is not actually active.
282 if (!usingKvm)
283 return Pl390::updateIntState(hint);
284}
285
286void
287MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
288 ContextID ctx, Addr daddr)
289{
290 auto val = from->readDistributor(ctx, daddr);
291 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
292 to->writeDistributor(ctx, daddr, val);
293}
294
295void
296MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
297 ContextID ctx, Addr daddr)
298{
299 auto val = from->readCpu(ctx, daddr);
300 DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
301 to->writeCpu(ctx, daddr, val);
302}
303
304void
305MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
306 Addr daddr, size_t size)
307{
| 1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 * Curtis Dunham
39 */
40
41#include "arch/arm/kvm/gic.hh"
42
43#include <linux/kvm.h>
44
45#include "arch/arm/kvm/base_cpu.hh"
46#include "debug/GIC.hh"
47#include "debug/Interrupt.hh"
48#include "params/MuxingKvmGic.hh"
49
50KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
51 unsigned it_lines)
52 : cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
53 distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)),
54 vm(_vm),
55 kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
56{
57 // Tell the VM that we will emulate the GIC in the kernel. This
58 // disables IRQ and FIQ handling in the KVM CPU model.
59 vm.enableKernelIRQChip();
60
61 kdev.setAttr<uint64_t>(
62 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
63 kdev.setAttr<uint64_t>(
64 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
65
66 kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
67}
68
69KvmKernelGicV2::~KvmKernelGicV2()
70{
71}
72
73void
74KvmKernelGicV2::setSPI(unsigned spi)
75{
76 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
77}
78
79void
80KvmKernelGicV2::clearSPI(unsigned spi)
81{
82 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
83}
84
85void
86KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
87{
88 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
89}
90
91void
92KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
93{
94 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
95}
96
97void
98KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
99 bool high)
100{
101 assert(type <= KVM_ARM_IRQ_TYPE_MASK);
102 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
103 assert(irq <= KVM_ARM_IRQ_NUM_MASK);
104 const uint32_t line(
105 (type << KVM_ARM_IRQ_TYPE_SHIFT) |
106 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
107 (irq << KVM_ARM_IRQ_NUM_SHIFT));
108
109 vm.setIRQLine(line, high);
110}
111
112uint32_t
113KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
114{
115 uint64_t reg;
116
117 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
118 const uint32_t attr(
119 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
120 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
121
122 kdev.getAttrPtr(group, attr, ®);
123 return (uint32_t) reg;
124}
125
126void
127KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
128 unsigned value)
129{
130 uint64_t reg = value;
131
132 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
133 const uint32_t attr(
134 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
135 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
136
137 kdev.setAttrPtr(group, attr, ®);
138}
139
140uint32_t
141KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
142{
143 auto vcpu = vm.contextIdToVCpuId(ctx);
144 return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
145}
146
147uint32_t
148KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
149{
150 auto vcpu = vm.contextIdToVCpuId(ctx);
151 return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
152}
153
154void
155KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
156{
157 auto vcpu = vm.contextIdToVCpuId(ctx);
158 setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
159}
160
161void
162KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
163{
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166}
167
168
169
170MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
171 : Pl390(p),
172 system(*p->system),
173 kernelGic(nullptr),
174 usingKvm(false)
175{
176 if (auto vm = system.getKvmVM()) {
177 kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
178 p->it_lines);
179 }
180}
181
182MuxingKvmGic::~MuxingKvmGic()
183{
184}
185
186void
187MuxingKvmGic::startup()
188{
189 Pl390::startup();
190 usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
191 if (usingKvm)
192 fromPl390ToKvm();
193}
194
195DrainState
196MuxingKvmGic::drain()
197{
198 if (usingKvm)
199 fromKvmToPl390();
200 return Pl390::drain();
201}
202
203void
204MuxingKvmGic::drainResume()
205{
206 Pl390::drainResume();
207 bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
208 if (use_kvm != usingKvm) {
209 // Should only occur due to CPU switches
210 if (use_kvm) // from simulation to KVM emulation
211 fromPl390ToKvm();
212 // otherwise, drain() already sync'd the state back to the Pl390
213
214 usingKvm = use_kvm;
215 }
216}
217
218Tick
219MuxingKvmGic::read(PacketPtr pkt)
220{
221 if (!usingKvm)
222 return Pl390::read(pkt);
223
224 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
225}
226
227Tick
228MuxingKvmGic::write(PacketPtr pkt)
229{
230 if (!usingKvm)
231 return Pl390::write(pkt);
232
233 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
234}
235
236void
237MuxingKvmGic::sendInt(uint32_t num)
238{
239 if (!usingKvm)
240 return Pl390::sendInt(num);
241
242 DPRINTF(Interrupt, "Set SPI %d\n", num);
243 kernelGic->setSPI(num);
244}
245
246void
247MuxingKvmGic::clearInt(uint32_t num)
248{
249 if (!usingKvm)
250 return Pl390::clearInt(num);
251
252 DPRINTF(Interrupt, "Clear SPI %d\n", num);
253 kernelGic->clearSPI(num);
254}
255
256void
257MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
258{
259 if (!usingKvm)
260 return Pl390::sendPPInt(num, cpu);
261 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
262 kernelGic->setPPI(cpu, num);
263}
264
265void
266MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
267{
268 if (!usingKvm)
269 return Pl390::clearPPInt(num, cpu);
270
271 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
272 kernelGic->clearPPI(cpu, num);
273}
274
275void
276MuxingKvmGic::updateIntState(int hint)
277{
278 // During Kvm->Pl390 state transfer, writes to the Pl390 will call
279 // updateIntState() which can post an interrupt. Since we're only
280 // using the Pl390 model for holding state in this circumstance, we
281 // short-circuit this behavior, as the Pl390 is not actually active.
282 if (!usingKvm)
283 return Pl390::updateIntState(hint);
284}
285
286void
287MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
288 ContextID ctx, Addr daddr)
289{
290 auto val = from->readDistributor(ctx, daddr);
291 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
292 to->writeDistributor(ctx, daddr, val);
293}
294
295void
296MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
297 ContextID ctx, Addr daddr)
298{
299 auto val = from->readCpu(ctx, daddr);
300 DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
301 to->writeCpu(ctx, daddr, val);
302}
303
304void
305MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
306 Addr daddr, size_t size)
307{
|
349 copyCpuRegister(from, to, ctx, GICC_CTLR);
350 copyCpuRegister(from, to, ctx, GICC_PMR);
351 copyCpuRegister(from, to, ctx, GICC_BPR);
352 }
353
354
355 /// Distributor state (GICD_*)
356 // Copy Distributor Control Register (CTLR)
357 copyDistRegister(from, to, 0, GICD_CTLR);
358
359 // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
360 set = Pl390::GICD_ISENABLER.start();
361 clear = Pl390::GICD_ICENABLER.start();
362 size = Pl390::itLines / 8;
363 clearBankedDistRange(to, clear, 4);
364 copyBankedDistRange(from, to, set, 4);
365
366 set += 4, clear += 4, size -= 4;
367 clearDistRange(to, clear, size);
368 copyDistRange(from, to, set, size);
369
370 // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
371 set = Pl390::GICD_ISPENDR.start();
372 clear = Pl390::GICD_ICPENDR.start();
373 size = Pl390::itLines / 8;
374 clearBankedDistRange(to, clear, 4);
375 copyBankedDistRange(from, to, set, 4);
376
377 set += 4, clear += 4, size -= 4;
378 clearDistRange(to, clear, size);
379 copyDistRange(from, to, set, size);
380
381 // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
382 set = Pl390::GICD_ISACTIVER.start();
383 clear = Pl390::GICD_ICACTIVER.start();
384 size = Pl390::itLines / 8;
385 clearBankedDistRange(to, clear, 4);
386 copyBankedDistRange(from, to, set, 4);
387
388 set += 4, clear += 4, size -= 4;
389 clearDistRange(to, clear, size);
390 copyDistRange(from, to, set, size);
391
392 // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
393 set = Pl390::GICD_IPRIORITYR.start();
394 copyBankedDistRange(from, to, set, 32);
395
396 set += 32;
397 size = Pl390::itLines - 32;
398 copyDistRange(from, to, set, size);
399
400 // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
401 set = Pl390::GICD_ITARGETSR.start() + 32;
402 size = Pl390::itLines - 32;
403 copyDistRange(from, to, set, size);
404
405 // Copy interrupt configuration registers (ICFGRn)
406 set = Pl390::GICD_ICFGR.start();
407 size = Pl390::itLines / 4;
408 copyDistRange(from, to, set, size);
409}
410
411void
412MuxingKvmGic::fromPl390ToKvm()
413{
414 copyGicState(static_cast<Pl390*>(this), kernelGic);
415}
416
417void
418MuxingKvmGic::fromKvmToPl390()
419{
420 copyGicState(kernelGic, static_cast<Pl390*>(this));
421
422 // the values read for the Interrupt Priority Mask Register (PMR)
423 // have been shifted by three bits due to its having been emulated by
424 // a VGIC with only 5 PMR bits in its VMCR register. Presently the
425 // Linux kernel does not repair this inaccuracy, so we correct it here.
| 349 copyCpuRegister(from, to, ctx, GICC_CTLR);
350 copyCpuRegister(from, to, ctx, GICC_PMR);
351 copyCpuRegister(from, to, ctx, GICC_BPR);
352 }
353
354
355 /// Distributor state (GICD_*)
356 // Copy Distributor Control Register (CTLR)
357 copyDistRegister(from, to, 0, GICD_CTLR);
358
359 // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
360 set = Pl390::GICD_ISENABLER.start();
361 clear = Pl390::GICD_ICENABLER.start();
362 size = Pl390::itLines / 8;
363 clearBankedDistRange(to, clear, 4);
364 copyBankedDistRange(from, to, set, 4);
365
366 set += 4, clear += 4, size -= 4;
367 clearDistRange(to, clear, size);
368 copyDistRange(from, to, set, size);
369
370 // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
371 set = Pl390::GICD_ISPENDR.start();
372 clear = Pl390::GICD_ICPENDR.start();
373 size = Pl390::itLines / 8;
374 clearBankedDistRange(to, clear, 4);
375 copyBankedDistRange(from, to, set, 4);
376
377 set += 4, clear += 4, size -= 4;
378 clearDistRange(to, clear, size);
379 copyDistRange(from, to, set, size);
380
381 // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
382 set = Pl390::GICD_ISACTIVER.start();
383 clear = Pl390::GICD_ICACTIVER.start();
384 size = Pl390::itLines / 8;
385 clearBankedDistRange(to, clear, 4);
386 copyBankedDistRange(from, to, set, 4);
387
388 set += 4, clear += 4, size -= 4;
389 clearDistRange(to, clear, size);
390 copyDistRange(from, to, set, size);
391
392 // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
393 set = Pl390::GICD_IPRIORITYR.start();
394 copyBankedDistRange(from, to, set, 32);
395
396 set += 32;
397 size = Pl390::itLines - 32;
398 copyDistRange(from, to, set, size);
399
400 // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
401 set = Pl390::GICD_ITARGETSR.start() + 32;
402 size = Pl390::itLines - 32;
403 copyDistRange(from, to, set, size);
404
405 // Copy interrupt configuration registers (ICFGRn)
406 set = Pl390::GICD_ICFGR.start();
407 size = Pl390::itLines / 4;
408 copyDistRange(from, to, set, size);
409}
410
411void
412MuxingKvmGic::fromPl390ToKvm()
413{
414 copyGicState(static_cast<Pl390*>(this), kernelGic);
415}
416
417void
418MuxingKvmGic::fromKvmToPl390()
419{
420 copyGicState(kernelGic, static_cast<Pl390*>(this));
421
422 // the values read for the Interrupt Priority Mask Register (PMR)
423 // have been shifted by three bits due to its having been emulated by
424 // a VGIC with only 5 PMR bits in its VMCR register. Presently the
425 // Linux kernel does not repair this inaccuracy, so we correct it here.
|