1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 * Curtis Dunham
39 */
40
41#include "arch/arm/kvm/gic.hh"
42
43#include <linux/kvm.h>
44
45#include "arch/arm/kvm/base_cpu.hh"
46#include "debug/GIC.hh"
47#include "debug/Interrupt.hh"
48#include "params/MuxingKvmGic.hh"
49
50KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
51 unsigned it_lines)
52 : cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
53 distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)),
54 vm(_vm),
55 kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
56{
57 // Tell the VM that we will emulate the GIC in the kernel. This
58 // disables IRQ and FIQ handling in the KVM CPU model.
59 vm.enableKernelIRQChip();
60
61 kdev.setAttr<uint64_t>(
62 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
63 kdev.setAttr<uint64_t>(
64 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
65
66 kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
67}
68
69KvmKernelGicV2::~KvmKernelGicV2()
70{
71}
72
73void
74KvmKernelGicV2::setSPI(unsigned spi)
75{
76 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
77}
78
79void
80KvmKernelGicV2::clearSPI(unsigned spi)
81{
82 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
83}
84
85void
86KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
87{
88 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
89}
90
91void
92KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
93{
94 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
95}
96
97void
98KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
99 bool high)
100{
101 assert(type <= KVM_ARM_IRQ_TYPE_MASK);
102 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
103 assert(irq <= KVM_ARM_IRQ_NUM_MASK);
104 const uint32_t line(
105 (type << KVM_ARM_IRQ_TYPE_SHIFT) |
106 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
107 (irq << KVM_ARM_IRQ_NUM_SHIFT));
108
109 vm.setIRQLine(line, high);
110}
111
112uint32_t
113KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
114{
115 uint64_t reg;
116
117 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
118 const uint32_t attr(
119 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
120 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
121
122 kdev.getAttrPtr(group, attr, ®);
123 return (uint32_t) reg;
124}
125
126void
127KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
128 unsigned value)
129{
130 uint64_t reg = value;
131
132 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
133 const uint32_t attr(
134 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
135 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
136
137 kdev.setAttrPtr(group, attr, ®);
138}
139
140uint32_t
141KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
142{
143 auto vcpu = vm.contextIdToVCpuId(ctx);
144 return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
145}
146
147uint32_t
148KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
149{
150 auto vcpu = vm.contextIdToVCpuId(ctx);
151 return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
152}
153
154void
155KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
156{
157 auto vcpu = vm.contextIdToVCpuId(ctx);
158 setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
159}
160
161void
162KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
163{
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166}
167
168
169
170MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
171 : Pl390(p),
172 system(*p->system),
173 kernelGic(nullptr),
174 usingKvm(false)
175{
176 if (auto vm = system.getKvmVM()) {
177 kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
178 p->it_lines);
179 }
180}
181
182MuxingKvmGic::~MuxingKvmGic()
183{
184}
185
186void
187MuxingKvmGic::loadState(CheckpointIn &cp)
188{
189 Pl390::loadState(cp);
190}
191
192void
193MuxingKvmGic::startup()
194{
195 Pl390::startup();
196 usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
197 if (usingKvm)
198 fromPl390ToKvm();
199}
200
201DrainState
202MuxingKvmGic::drain()
203{
204 if (usingKvm)
205 fromKvmToPl390();
206 return Pl390::drain();
207}
208
209void
210MuxingKvmGic::drainResume()
211{
212 Pl390::drainResume();
213 bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
214 if (use_kvm != usingKvm) {
215 // Should only occur due to CPU switches
216 if (use_kvm) // from simulation to KVM emulation
217 fromPl390ToKvm();
218 // otherwise, drain() already sync'd the state back to the Pl390
219
220 usingKvm = use_kvm;
221 }
222}
223
224void
225MuxingKvmGic::serialize(CheckpointOut &cp) const
226{
227 // drain() already ensured Pl390 updated with KvmGic state if necessary
228 Pl390::serialize(cp);
229}
230
231void
232MuxingKvmGic::unserialize(CheckpointIn &cp)
233{
234 Pl390::unserialize(cp);
235}
236
237Tick
238MuxingKvmGic::read(PacketPtr pkt)
239{
240 if (!usingKvm)
241 return Pl390::read(pkt);
242
243 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
244}
245
246Tick
247MuxingKvmGic::write(PacketPtr pkt)
248{
249 if (!usingKvm)
250 return Pl390::write(pkt);
251
252 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
253}
254
255void
256MuxingKvmGic::sendInt(uint32_t num)
257{
258 if (!usingKvm)
259 return Pl390::sendInt(num);
260
261 DPRINTF(Interrupt, "Set SPI %d\n", num);
262 kernelGic->setSPI(num);
263}
264
265void
266MuxingKvmGic::clearInt(uint32_t num)
267{
268 if (!usingKvm)
269 return Pl390::clearInt(num);
270
271 DPRINTF(Interrupt, "Clear SPI %d\n", num);
272 kernelGic->clearSPI(num);
273}
274
275void
276MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
277{
278 if (!usingKvm)
279 return Pl390::sendPPInt(num, cpu);
280 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
281 kernelGic->setPPI(cpu, num);
282}
283
284void
285MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
286{
287 if (!usingKvm)
288 return Pl390::clearPPInt(num, cpu);
289
290 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
291 kernelGic->clearPPI(cpu, num);
292}
293
294void
| 1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 * Curtis Dunham
39 */
40
41#include "arch/arm/kvm/gic.hh"
42
43#include <linux/kvm.h>
44
45#include "arch/arm/kvm/base_cpu.hh"
46#include "debug/GIC.hh"
47#include "debug/Interrupt.hh"
48#include "params/MuxingKvmGic.hh"
49
50KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
51 unsigned it_lines)
52 : cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
53 distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)),
54 vm(_vm),
55 kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
56{
57 // Tell the VM that we will emulate the GIC in the kernel. This
58 // disables IRQ and FIQ handling in the KVM CPU model.
59 vm.enableKernelIRQChip();
60
61 kdev.setAttr<uint64_t>(
62 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
63 kdev.setAttr<uint64_t>(
64 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
65
66 kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
67}
68
69KvmKernelGicV2::~KvmKernelGicV2()
70{
71}
72
73void
74KvmKernelGicV2::setSPI(unsigned spi)
75{
76 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
77}
78
79void
80KvmKernelGicV2::clearSPI(unsigned spi)
81{
82 setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
83}
84
85void
86KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
87{
88 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
89}
90
91void
92KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
93{
94 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
95}
96
97void
98KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
99 bool high)
100{
101 assert(type <= KVM_ARM_IRQ_TYPE_MASK);
102 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
103 assert(irq <= KVM_ARM_IRQ_NUM_MASK);
104 const uint32_t line(
105 (type << KVM_ARM_IRQ_TYPE_SHIFT) |
106 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
107 (irq << KVM_ARM_IRQ_NUM_SHIFT));
108
109 vm.setIRQLine(line, high);
110}
111
112uint32_t
113KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
114{
115 uint64_t reg;
116
117 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
118 const uint32_t attr(
119 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
120 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
121
122 kdev.getAttrPtr(group, attr, ®);
123 return (uint32_t) reg;
124}
125
126void
127KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
128 unsigned value)
129{
130 uint64_t reg = value;
131
132 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
133 const uint32_t attr(
134 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
135 (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
136
137 kdev.setAttrPtr(group, attr, ®);
138}
139
140uint32_t
141KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
142{
143 auto vcpu = vm.contextIdToVCpuId(ctx);
144 return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
145}
146
147uint32_t
148KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
149{
150 auto vcpu = vm.contextIdToVCpuId(ctx);
151 return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
152}
153
154void
155KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
156{
157 auto vcpu = vm.contextIdToVCpuId(ctx);
158 setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
159}
160
161void
162KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
163{
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166}
167
168
169
170MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
171 : Pl390(p),
172 system(*p->system),
173 kernelGic(nullptr),
174 usingKvm(false)
175{
176 if (auto vm = system.getKvmVM()) {
177 kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
178 p->it_lines);
179 }
180}
181
182MuxingKvmGic::~MuxingKvmGic()
183{
184}
185
186void
187MuxingKvmGic::loadState(CheckpointIn &cp)
188{
189 Pl390::loadState(cp);
190}
191
192void
193MuxingKvmGic::startup()
194{
195 Pl390::startup();
196 usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
197 if (usingKvm)
198 fromPl390ToKvm();
199}
200
201DrainState
202MuxingKvmGic::drain()
203{
204 if (usingKvm)
205 fromKvmToPl390();
206 return Pl390::drain();
207}
208
209void
210MuxingKvmGic::drainResume()
211{
212 Pl390::drainResume();
213 bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
214 if (use_kvm != usingKvm) {
215 // Should only occur due to CPU switches
216 if (use_kvm) // from simulation to KVM emulation
217 fromPl390ToKvm();
218 // otherwise, drain() already sync'd the state back to the Pl390
219
220 usingKvm = use_kvm;
221 }
222}
223
224void
225MuxingKvmGic::serialize(CheckpointOut &cp) const
226{
227 // drain() already ensured Pl390 updated with KvmGic state if necessary
228 Pl390::serialize(cp);
229}
230
231void
232MuxingKvmGic::unserialize(CheckpointIn &cp)
233{
234 Pl390::unserialize(cp);
235}
236
237Tick
238MuxingKvmGic::read(PacketPtr pkt)
239{
240 if (!usingKvm)
241 return Pl390::read(pkt);
242
243 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
244}
245
246Tick
247MuxingKvmGic::write(PacketPtr pkt)
248{
249 if (!usingKvm)
250 return Pl390::write(pkt);
251
252 panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
253}
254
255void
256MuxingKvmGic::sendInt(uint32_t num)
257{
258 if (!usingKvm)
259 return Pl390::sendInt(num);
260
261 DPRINTF(Interrupt, "Set SPI %d\n", num);
262 kernelGic->setSPI(num);
263}
264
265void
266MuxingKvmGic::clearInt(uint32_t num)
267{
268 if (!usingKvm)
269 return Pl390::clearInt(num);
270
271 DPRINTF(Interrupt, "Clear SPI %d\n", num);
272 kernelGic->clearSPI(num);
273}
274
275void
276MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
277{
278 if (!usingKvm)
279 return Pl390::sendPPInt(num, cpu);
280 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
281 kernelGic->setPPI(cpu, num);
282}
283
284void
285MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
286{
287 if (!usingKvm)
288 return Pl390::clearPPInt(num, cpu);
289
290 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
291 kernelGic->clearPPI(cpu, num);
292}
293
294void
|
| 295MuxingKvmGic::updateIntState(int hint)
296{
297 // During Kvm->Pl390 state transfer, writes to the Pl390 will call
298 // updateIntState() which can post an interrupt. Since we're only
299 // using the Pl390 model for holding state in this circumstance, we
300 // short-circuit this behavior, as the Pl390 is not actually active.
301 if (!usingKvm)
302 return Pl390::updateIntState(hint);
303}
304
305void
|
295MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
296 ContextID ctx, Addr daddr)
297{
298 auto val = from->readDistributor(ctx, daddr);
299 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
300 to->writeDistributor(ctx, daddr, val);
301}
302
303void
304MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
305 ContextID ctx, Addr daddr)
306{
307 auto val = from->readCpu(ctx, daddr);
308 DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
309 to->writeCpu(ctx, daddr, val);
310}
311
312void
313MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
314 Addr daddr, size_t size)
315{
316 for (int ctx = 0; ctx < system._numContexts; ++ctx)
317 for (auto a = daddr; a < daddr + size; a += 4)
318 copyDistRegister(from, to, ctx, a);
319}
320
321void
322MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
323 Addr daddr, size_t size)
324{
325 for (int ctx = 0; ctx < system._numContexts; ++ctx)
326 for (auto a = daddr; a < daddr + size; a += 4)
327 to->writeDistributor(ctx, a, 0xFFFFFFFF);
328}
329
330void
331MuxingKvmGic::copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
332 Addr daddr, size_t size)
333{
334 for (auto a = daddr; a < daddr + size; a += 4)
335 copyDistRegister(from, to, 0, a);
336}
337
338void
339MuxingKvmGic::clearDistRange(BaseGicRegisters* to,
340 Addr daddr, size_t size)
341{
342 for (auto a = daddr; a < daddr + size; a += 4)
343 to->writeDistributor(0, a, 0xFFFFFFFF);
344}
345
346void
347MuxingKvmGic::copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
348{
349 Addr set, clear;
350 size_t size;
351
352 /// CPU state (GICC_*)
353 // Copy CPU Interface Control Register (CTLR),
354 // Interrupt Priority Mask Register (PMR), and
355 // Binary Point Register (BPR)
356 for (int ctx = 0; ctx < system._numContexts; ++ctx) {
357 copyCpuRegister(from, to, ctx, GICC_CTLR);
358 copyCpuRegister(from, to, ctx, GICC_PMR);
359 copyCpuRegister(from, to, ctx, GICC_BPR);
360 }
361
362
363 /// Distributor state (GICD_*)
364 // Copy Distributor Control Register (CTLR)
365 copyDistRegister(from, to, 0, GICD_CTLR);
366
367 // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
368 set = Pl390::GICD_ISENABLER.start();
369 clear = Pl390::GICD_ICENABLER.start();
370 size = Pl390::itLines / 8;
371 clearBankedDistRange(to, clear, 4);
372 copyBankedDistRange(from, to, set, 4);
373
374 set += 4, clear += 4, size -= 4;
375 clearDistRange(to, clear, size);
376 copyDistRange(from, to, set, size);
377
378 // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
379 set = Pl390::GICD_ISPENDR.start();
380 clear = Pl390::GICD_ICPENDR.start();
381 size = Pl390::itLines / 8;
382 clearBankedDistRange(to, clear, 4);
383 copyBankedDistRange(from, to, set, 4);
384
385 set += 4, clear += 4, size -= 4;
386 clearDistRange(to, clear, size);
387 copyDistRange(from, to, set, size);
388
389 // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
390 set = Pl390::GICD_ISACTIVER.start();
391 clear = Pl390::GICD_ICACTIVER.start();
392 size = Pl390::itLines / 8;
393 clearBankedDistRange(to, clear, 4);
394 copyBankedDistRange(from, to, set, 4);
395
396 set += 4, clear += 4, size -= 4;
397 clearDistRange(to, clear, size);
398 copyDistRange(from, to, set, size);
399
400 // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
401 set = Pl390::GICD_IPRIORITYR.start();
402 copyBankedDistRange(from, to, set, 32);
403
404 set += 32;
405 size = Pl390::itLines - 32;
406 copyDistRange(from, to, set, size);
407
408 // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
409 set = Pl390::GICD_ITARGETSR.start() + 32;
410 size = Pl390::itLines - 32;
411 copyDistRange(from, to, set, size);
412
413 // Copy interrupt configuration registers (ICFGRn)
414 set = Pl390::GICD_ICFGR.start();
415 size = Pl390::itLines / 4;
416 copyDistRange(from, to, set, size);
417}
418
419void
420MuxingKvmGic::fromPl390ToKvm()
421{
422 copyGicState(static_cast<Pl390*>(this), kernelGic);
423}
424
425void
426MuxingKvmGic::fromKvmToPl390()
427{
428 copyGicState(kernelGic, static_cast<Pl390*>(this));
429
430 // the values read for the Interrupt Priority Mask Register (PMR)
431 // have been shifted by three bits due to its having been emulated by
432 // a VGIC with only 5 PMR bits in its VMCR register. Presently the
433 // Linux kernel does not repair this inaccuracy, so we correct it here.
434 for (int cpu = 0; cpu < system._numContexts; ++cpu) {
435 cpuPriority[cpu] <<= 3;
436 assert((cpuPriority[cpu] & ~0xff) == 0);
437 }
438}
439
440MuxingKvmGic *
441MuxingKvmGicParams::create()
442{
443 return new MuxingKvmGic(this);
444}
| 306MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
307 ContextID ctx, Addr daddr)
308{
309 auto val = from->readDistributor(ctx, daddr);
310 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
311 to->writeDistributor(ctx, daddr, val);
312}
313
314void
315MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
316 ContextID ctx, Addr daddr)
317{
318 auto val = from->readCpu(ctx, daddr);
319 DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
320 to->writeCpu(ctx, daddr, val);
321}
322
323void
324MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
325 Addr daddr, size_t size)
326{
327 for (int ctx = 0; ctx < system._numContexts; ++ctx)
328 for (auto a = daddr; a < daddr + size; a += 4)
329 copyDistRegister(from, to, ctx, a);
330}
331
332void
333MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
334 Addr daddr, size_t size)
335{
336 for (int ctx = 0; ctx < system._numContexts; ++ctx)
337 for (auto a = daddr; a < daddr + size; a += 4)
338 to->writeDistributor(ctx, a, 0xFFFFFFFF);
339}
340
341void
342MuxingKvmGic::copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
343 Addr daddr, size_t size)
344{
345 for (auto a = daddr; a < daddr + size; a += 4)
346 copyDistRegister(from, to, 0, a);
347}
348
349void
350MuxingKvmGic::clearDistRange(BaseGicRegisters* to,
351 Addr daddr, size_t size)
352{
353 for (auto a = daddr; a < daddr + size; a += 4)
354 to->writeDistributor(0, a, 0xFFFFFFFF);
355}
356
357void
358MuxingKvmGic::copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
359{
360 Addr set, clear;
361 size_t size;
362
363 /// CPU state (GICC_*)
364 // Copy CPU Interface Control Register (CTLR),
365 // Interrupt Priority Mask Register (PMR), and
366 // Binary Point Register (BPR)
367 for (int ctx = 0; ctx < system._numContexts; ++ctx) {
368 copyCpuRegister(from, to, ctx, GICC_CTLR);
369 copyCpuRegister(from, to, ctx, GICC_PMR);
370 copyCpuRegister(from, to, ctx, GICC_BPR);
371 }
372
373
374 /// Distributor state (GICD_*)
375 // Copy Distributor Control Register (CTLR)
376 copyDistRegister(from, to, 0, GICD_CTLR);
377
378 // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
379 set = Pl390::GICD_ISENABLER.start();
380 clear = Pl390::GICD_ICENABLER.start();
381 size = Pl390::itLines / 8;
382 clearBankedDistRange(to, clear, 4);
383 copyBankedDistRange(from, to, set, 4);
384
385 set += 4, clear += 4, size -= 4;
386 clearDistRange(to, clear, size);
387 copyDistRange(from, to, set, size);
388
389 // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
390 set = Pl390::GICD_ISPENDR.start();
391 clear = Pl390::GICD_ICPENDR.start();
392 size = Pl390::itLines / 8;
393 clearBankedDistRange(to, clear, 4);
394 copyBankedDistRange(from, to, set, 4);
395
396 set += 4, clear += 4, size -= 4;
397 clearDistRange(to, clear, size);
398 copyDistRange(from, to, set, size);
399
400 // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
401 set = Pl390::GICD_ISACTIVER.start();
402 clear = Pl390::GICD_ICACTIVER.start();
403 size = Pl390::itLines / 8;
404 clearBankedDistRange(to, clear, 4);
405 copyBankedDistRange(from, to, set, 4);
406
407 set += 4, clear += 4, size -= 4;
408 clearDistRange(to, clear, size);
409 copyDistRange(from, to, set, size);
410
411 // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
412 set = Pl390::GICD_IPRIORITYR.start();
413 copyBankedDistRange(from, to, set, 32);
414
415 set += 32;
416 size = Pl390::itLines - 32;
417 copyDistRange(from, to, set, size);
418
419 // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
420 set = Pl390::GICD_ITARGETSR.start() + 32;
421 size = Pl390::itLines - 32;
422 copyDistRange(from, to, set, size);
423
424 // Copy interrupt configuration registers (ICFGRn)
425 set = Pl390::GICD_ICFGR.start();
426 size = Pl390::itLines / 4;
427 copyDistRange(from, to, set, size);
428}
429
430void
431MuxingKvmGic::fromPl390ToKvm()
432{
433 copyGicState(static_cast<Pl390*>(this), kernelGic);
434}
435
436void
437MuxingKvmGic::fromKvmToPl390()
438{
439 copyGicState(kernelGic, static_cast<Pl390*>(this));
440
441 // the values read for the Interrupt Priority Mask Register (PMR)
442 // have been shifted by three bits due to its having been emulated by
443 // a VGIC with only 5 PMR bits in its VMCR register. Presently the
444 // Linux kernel does not repair this inaccuracy, so we correct it here.
445 for (int cpu = 0; cpu < system._numContexts; ++cpu) {
446 cpuPriority[cpu] <<= 3;
447 assert((cpuPriority[cpu] & ~0xff) == 0);
448 }
449}
450
451MuxingKvmGic *
452MuxingKvmGicParams::create()
453{
454 return new MuxingKvmGic(this);
455}
|