armv8_cpu.cc (12156:5ca7617f41b3) armv8_cpu.cc (13544:0b4e5446167c)
1/*
2 * Copyright (c) 2015, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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91 uint64_t i;
92 double f;
93 } d[2];
94
95 uint8_t data[32];
96};
97
98#define FP_REGS_PER_VFP_REG 4
1/*
2 * Copyright (c) 2015, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 82 unchanged lines hidden (view full) ---

91 uint64_t i;
92 double f;
93 } d[2];
94
95 uint8_t data[32];
96};
97
98#define FP_REGS_PER_VFP_REG 4
99static_assert(sizeof(FloatRegBits) == 4, "Unexpected float reg size");
100
101const std::vector<ArmV8KvmCPU::IntRegInfo> ArmV8KvmCPU::intRegMap = {
102 { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
103 { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
104};
105
106const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = {
107 MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),

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100const std::vector<ArmV8KvmCPU::IntRegInfo> ArmV8KvmCPU::intRegMap = {
101 { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
102 { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
103};
104
105const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = {
106 MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),

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