arm_cpu.cc (10857:d2d5212578db) arm_cpu.cc (11178:555325cbf464)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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265 * starts to support more CPUs.
266 */
267 kvmArmVCpuInit(KVM_ARM_TARGET_CORTEX_A15);
268}
269
270Tick
271ArmKvmCPU::kvmRun(Tick ticks)
272{
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 256 unchanged lines hidden (view full) ---

265 * starts to support more CPUs.
266 */
267 kvmArmVCpuInit(KVM_ARM_TARGET_CORTEX_A15);
268}
269
270Tick
271ArmKvmCPU::kvmRun(Tick ticks)
272{
273 bool simFIQ(interrupts->checkRaw(INT_FIQ));
274 bool simIRQ(interrupts->checkRaw(INT_IRQ));
273 bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
274 bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
275
276 if (fiqAsserted != simFIQ) {
277 fiqAsserted = simFIQ;
278 DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
279 vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
280 }
281 if (irqAsserted != simIRQ) {
282 irqAsserted = simIRQ;

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276 if (fiqAsserted != simFIQ) {
277 fiqAsserted = simFIQ;
278 DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
279 vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
280 }
281 if (irqAsserted != simIRQ) {
282 irqAsserted = simIRQ;

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