isa_traits.hh (9329:3fe8438cbcfc) | isa_traits.hh (10037:5cac77888310) |
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1/* | 1/* |
2 * Copyright (c) 2010 ARM Limited | 2 * Copyright (c) 2010, 2012 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 79 unchanged lines hidden (view full) --- 90 const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 91 const Addr VAddrUnImplMask = ~VAddrImplMask; 92 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 93 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 94 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 95 96 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 97 | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 79 unchanged lines hidden (view full) --- 90 const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 91 const Addr VAddrUnImplMask = ~VAddrImplMask; 92 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 93 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 94 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 95 96 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 97 |
98 // Max. physical address range in bits supported by the architecture 99 const unsigned MaxPhysAddrRange = 48; 100 |
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98 // return a no-op instruction... used for instruction fetch faults 99 const ExtMachInst NoopMachInst = 0x01E320F000ULL; 100 101 const int LogVMPageSize = 12; // 4K bytes 102 const int VMPageSize = (1 << LogVMPageSize); 103 104 // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali 105 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned --- 13 unchanged lines hidden (view full) --- 119 120 enum InterruptTypes 121 { 122 INT_RST, 123 INT_ABT, 124 INT_IRQ, 125 INT_FIQ, 126 INT_SEV, // Special interrupt for recieving SEV's | 101 // return a no-op instruction... used for instruction fetch faults 102 const ExtMachInst NoopMachInst = 0x01E320F000ULL; 103 104 const int LogVMPageSize = 12; // 4K bytes 105 const int VMPageSize = (1 << LogVMPageSize); 106 107 // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali 108 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned --- 13 unchanged lines hidden (view full) --- 122 123 enum InterruptTypes 124 { 125 INT_RST, 126 INT_ABT, 127 INT_IRQ, 128 INT_FIQ, 129 INT_SEV, // Special interrupt for recieving SEV's |
130 INT_VIRT_IRQ, 131 INT_VIRT_FIQ, |
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127 NumInterruptTypes 128 }; 129} // namespace ArmISA 130 131using namespace ArmISA; 132 133#endif // __ARCH_ARM_ISA_TRAITS_HH__ | 132 NumInterruptTypes 133 }; 134} // namespace ArmISA 135 136using namespace ArmISA; 137 138#endif // __ARCH_ARM_ISA_TRAITS_HH__ |