isa_traits.hh (6323:fd0f91f067d2) | isa_traits.hh (6329:5d8b91875859) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Gabe Black 30 * Stephen Hines 31 */ 32 33#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 34#define __ARCH_ARM_ISA_TRAITS_HH__ 35 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Gabe Black 30 * Stephen Hines 31 */ 32 33#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 34#define __ARCH_ARM_ISA_TRAITS_HH__ 35 |
36#include "arch/arm/max_inst_regs.hh" | |
37#include "arch/arm/types.hh" 38#include "base/types.hh" 39 40namespace LittleEndianGuest {}; 41 42#define TARGET_ARM 43 44class StaticInstPtr; 45 46namespace ArmISA 47{ 48 using namespace LittleEndianGuest; | 36#include "arch/arm/types.hh" 37#include "base/types.hh" 38 39namespace LittleEndianGuest {}; 40 41#define TARGET_ARM 42 43class StaticInstPtr; 44 45namespace ArmISA 46{ 47 using namespace LittleEndianGuest; |
49 using ArmISAInst::MaxInstSrcRegs; 50 using ArmISAInst::MaxInstDestRegs; | |
51 52 StaticInstPtr decodeInst(ExtMachInst); 53 54 // ARM DOES NOT have a delay slot 55 #define ISA_HAS_DELAY_SLOT 0 56 57 const Addr PageShift = 12; 58 const Addr PageBytes = ULL(1) << PageShift; --- 34 unchanged lines hidden (view full) --- 93 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 94 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 95 96 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 97 98 // return a no-op instruction... used for instruction fetch faults 99 const ExtMachInst NoopMachInst = 0x00000000; 100 | 48 49 StaticInstPtr decodeInst(ExtMachInst); 50 51 // ARM DOES NOT have a delay slot 52 #define ISA_HAS_DELAY_SLOT 0 53 54 const Addr PageShift = 12; 55 const Addr PageBytes = ULL(1) << PageShift; --- 34 unchanged lines hidden (view full) --- 90 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 91 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 92 93 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 94 95 // return a no-op instruction... used for instruction fetch faults 96 const ExtMachInst NoopMachInst = 0x00000000; 97 |
101 // Constants Related to the number of registers 102 const int NumIntArchRegs = 16; 103 const int NumIntSpecialRegs = 19; 104 const int NumFloatArchRegs = 16; 105 const int NumFloatSpecialRegs = 5; 106 const int NumInternalProcRegs = 0; 107 108 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 109 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 110 111 // semantically meaningful register indices 112 const int ReturnValueReg = 0; 113 const int ReturnValueReg1 = 1; 114 const int ReturnValueReg2 = 2; 115 const int ArgumentReg0 = 0; 116 const int ArgumentReg1 = 1; 117 const int ArgumentReg2 = 2; 118 const int ArgumentReg3 = 3; 119 const int FramePointerReg = 11; 120 const int StackPointerReg = 13; 121 const int ReturnAddressReg = 14; 122 const int PCReg = 15; 123 124 const int ZeroReg = NumIntArchRegs; 125 const int AddrReg = ZeroReg + 1; // Used to generate address for uops 126 127 const int SyscallNumReg = ReturnValueReg; 128 const int SyscallPseudoReturnReg = ReturnValueReg; 129 const int SyscallSuccessReg = ReturnValueReg; 130 | |
131 const int LogVMPageSize = 12; // 4K bytes 132 const int VMPageSize = (1 << LogVMPageSize); 133 134 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 135 136 const int MachineBytes = 4; 137 const int WordBytes = 4; 138 const int HalfwordBytes = 2; 139 const int ByteBytes = 1; | 98 const int LogVMPageSize = 12; // 4K bytes 99 const int VMPageSize = (1 << LogVMPageSize); 100 101 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 102 103 const int MachineBytes = 4; 104 const int WordBytes = 4; 105 const int HalfwordBytes = 2; 106 const int ByteBytes = 1; |
140 141 // These help enumerate all the registers for dependence tracking. 142 const int FP_Base_DepTag = NumIntRegs; 143 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; | |
144}; 145 146using namespace ArmISA; 147 148#endif // __ARCH_ARM_ISA_TRAITS_HH__ | 107}; 108 109using namespace ArmISA; 110 111#endif // __ARCH_ARM_ISA_TRAITS_HH__ |