isa_traits.hh (6214:1ec0ec8933ae) isa_traits.hh (6323:fd0f91f067d2)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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28 *
29 * Authors: Gabe Black
30 * Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_ISA_TRAITS_HH__
34#define __ARCH_ARM_ISA_TRAITS_HH__
35
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 19 unchanged lines hidden (view full) ---

28 *
29 * Authors: Gabe Black
30 * Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_ISA_TRAITS_HH__
34#define __ARCH_ARM_ISA_TRAITS_HH__
35
36#include "arch/arm/max_inst_regs.hh"
36#include "arch/arm/types.hh"
37#include "base/types.hh"
38
39namespace LittleEndianGuest {};
40
41#define TARGET_ARM
42
43class StaticInstPtr;
44
45namespace ArmISA
46{
47 using namespace LittleEndianGuest;
37#include "arch/arm/types.hh"
38#include "base/types.hh"
39
40namespace LittleEndianGuest {};
41
42#define TARGET_ARM
43
44class StaticInstPtr;
45
46namespace ArmISA
47{
48 using namespace LittleEndianGuest;
49 using ArmISAInst::MaxInstSrcRegs;
50 using ArmISAInst::MaxInstDestRegs;
48
49 StaticInstPtr decodeInst(ExtMachInst);
50
51 // ARM DOES NOT have a delay slot
52 #define ISA_HAS_DELAY_SLOT 0
53
54 const Addr PageShift = 12;
55 const Addr PageBytes = ULL(1) << PageShift;

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95 // return a no-op instruction... used for instruction fetch faults
96 const ExtMachInst NoopMachInst = 0x00000000;
97
98 // Constants Related to the number of registers
99 const int NumIntArchRegs = 16;
100 const int NumIntSpecialRegs = 19;
101 const int NumFloatArchRegs = 16;
102 const int NumFloatSpecialRegs = 5;
51
52 StaticInstPtr decodeInst(ExtMachInst);
53
54 // ARM DOES NOT have a delay slot
55 #define ISA_HAS_DELAY_SLOT 0
56
57 const Addr PageShift = 12;
58 const Addr PageBytes = ULL(1) << PageShift;

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98 // return a no-op instruction... used for instruction fetch faults
99 const ExtMachInst NoopMachInst = 0x00000000;
100
101 // Constants Related to the number of registers
102 const int NumIntArchRegs = 16;
103 const int NumIntSpecialRegs = 19;
104 const int NumFloatArchRegs = 16;
105 const int NumFloatSpecialRegs = 5;
103 const int NumControlRegs = 7;
104 const int NumInternalProcRegs = 0;
105
106 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
107 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
106 const int NumInternalProcRegs = 0;
107
108 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
109 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
108 const int NumMiscRegs = NumControlRegs;
109
110
110 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
111
112 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
113
114 // Static instruction parameters
115 const int MaxInstSrcRegs = 5;
116 const int MaxInstDestRegs = 3;
117
118 // semantically meaningful register indices
119 const int ReturnValueReg = 0;
120 const int ReturnValueReg1 = 1;
121 const int ReturnValueReg2 = 2;
122 const int ArgumentReg0 = 0;
123 const int ArgumentReg1 = 1;
124 const int ArgumentReg2 = 2;
125 const int ArgumentReg3 = 3;

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112 const int ReturnValueReg = 0;
113 const int ReturnValueReg1 = 1;
114 const int ReturnValueReg2 = 2;
115 const int ArgumentReg0 = 0;
116 const int ArgumentReg1 = 1;
117 const int ArgumentReg2 = 2;
118 const int ArgumentReg3 = 3;

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