isa_traits.hh (10037:5cac77888310) isa_traits.hh (10318:98771a936b61)
1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#define __ARCH_ARM_ISA_TRAITS_HH__
47
48#include "arch/arm/types.hh"
49#include "base/types.hh"
50#include "cpu/static_inst_fwd.hh"
51
52namespace LittleEndianGuest {}
53
1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#define __ARCH_ARM_ISA_TRAITS_HH__
47
48#include "arch/arm/types.hh"
49#include "base/types.hh"
50#include "cpu/static_inst_fwd.hh"
51
52namespace LittleEndianGuest {}
53
54#define TARGET_ARM
55
56namespace ArmISA
57{
58 using namespace LittleEndianGuest;
59
60 StaticInstPtr decodeInst(ExtMachInst);
61
62 // ARM DOES NOT have a delay slot
63 #define ISA_HAS_DELAY_SLOT 0

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96 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
97
98 // Max. physical address range in bits supported by the architecture
99 const unsigned MaxPhysAddrRange = 48;
100
101 // return a no-op instruction... used for instruction fetch faults
102 const ExtMachInst NoopMachInst = 0x01E320F000ULL;
103
54namespace ArmISA
55{
56 using namespace LittleEndianGuest;
57
58 StaticInstPtr decodeInst(ExtMachInst);
59
60 // ARM DOES NOT have a delay slot
61 #define ISA_HAS_DELAY_SLOT 0

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94 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
95
96 // Max. physical address range in bits supported by the architecture
97 const unsigned MaxPhysAddrRange = 48;
98
99 // return a no-op instruction... used for instruction fetch faults
100 const ExtMachInst NoopMachInst = 0x01E320F000ULL;
101
104 const int LogVMPageSize = 12; // 4K bytes
105 const int VMPageSize = (1 << LogVMPageSize);
106
107 // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
108 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
109
110 const int MachineBytes = 4;
102 const int MachineBytes = 4;
111 const int WordBytes = 4;
112 const int HalfwordBytes = 2;
113 const int ByteBytes = 1;
114
115 const uint32_t HighVecs = 0xFFFF0000;
116
117 // Memory accesses cannot be unaligned
118 const bool HasUnalignedMemAcc = true;
119
120 const bool CurThreadInfoImplemented = false;
121 const int CurThreadInfoReg = -1;

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104 const uint32_t HighVecs = 0xFFFF0000;
105
106 // Memory accesses cannot be unaligned
107 const bool HasUnalignedMemAcc = true;
108
109 const bool CurThreadInfoImplemented = false;
110 const int CurThreadInfoReg = -1;

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