1/* 2 * Copyright (c) 2010, 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 37 unchanged lines hidden (view full) --- 46#define __ARCH_ARM_ISA_TRAITS_HH__ 47 48#include "arch/arm/types.hh" 49#include "base/types.hh" 50#include "cpu/static_inst_fwd.hh" 51 52namespace LittleEndianGuest {} 53 |
54namespace ArmISA 55{ 56 using namespace LittleEndianGuest; 57 58 StaticInstPtr decodeInst(ExtMachInst); 59 60 // ARM DOES NOT have a delay slot 61 #define ISA_HAS_DELAY_SLOT 0 --- 32 unchanged lines hidden (view full) --- 94 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 95 96 // Max. physical address range in bits supported by the architecture 97 const unsigned MaxPhysAddrRange = 48; 98 99 // return a no-op instruction... used for instruction fetch faults 100 const ExtMachInst NoopMachInst = 0x01E320F000ULL; 101 |
102 const int MachineBytes = 4; |
103 104 const uint32_t HighVecs = 0xFFFF0000; 105 106 // Memory accesses cannot be unaligned 107 const bool HasUnalignedMemAcc = true; 108 109 const bool CurThreadInfoImplemented = false; 110 const int CurThreadInfoReg = -1; --- 17 unchanged lines hidden --- |