2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black 30 * Stephen Hines 31 */ 32 33#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 34#define __ARCH_ARM_ISA_TRAITS_HH__ 35 36#include "arch/arm/types.hh" 37#include "base/types.hh" 38 39namespace LittleEndianGuest {}; 40 41#define TARGET_ARM 42 43class StaticInstPtr; 44 45namespace ArmISA 46{ 47 using namespace LittleEndianGuest; 48 49 StaticInstPtr decodeInst(ExtMachInst); 50 51 // ARM DOES NOT have a delay slot 52 #define ISA_HAS_DELAY_SLOT 0 53 54 const Addr PageShift = 12; 55 const Addr PageBytes = ULL(1) << PageShift; 56 const Addr Page_Mask = ~(PageBytes - 1); 57 const Addr PageOffset = PageBytes - 1; 58 59 60 //////////////////////////////////////////////////////////////////////// 61 // 62 // Translation stuff 63 // 64 65 const Addr PteShift = 3; 66 const Addr NPtePageShift = PageShift - PteShift; 67 const Addr NPtePage = ULL(1) << NPtePageShift; 68 const Addr PteMask = NPtePage - 1; 69 70 //// All 'Mapped' segments go through the TLB 71 //// All other segments are translated by dropping the MSB, to give 72 //// the corresponding physical address 73 // User Segment - Mapped 74 const Addr USegBase = ULL(0x0); 75 const Addr USegEnd = ULL(0x7FFFFFFF); 76 77 // Kernel Segment 0 - Unmapped 78 const Addr KSeg0End = ULL(0x9FFFFFFF); 79 const Addr KSeg0Base = ULL(0x80000000); 80 const Addr KSeg0Mask = ULL(0x1FFFFFFF); 81 82 // For loading... XXX This maybe could be USegEnd?? --ali 83 const Addr LoadAddrMask = ULL(0xffffffffff); 84 85 const unsigned VABits = 32; 86 const unsigned PABits = 32; // Is this correct? 87 const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 88 const Addr VAddrUnImplMask = ~VAddrImplMask; 89 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 90 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 91 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 92 93 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 94 95 // return a no-op instruction... used for instruction fetch faults 96 const ExtMachInst NoopMachInst = 0x00000000; 97 98 const int LogVMPageSize = 12; // 4K bytes 99 const int VMPageSize = (1 << LogVMPageSize); 100 101 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 102 103 const int MachineBytes = 4; 104 const int WordBytes = 4; 105 const int HalfwordBytes = 2; 106 const int ByteBytes = 1; 107 108 const uint32_t HighVecs = 0xFFFF0000; 109 110 // Memory accesses cannot be unaligned 111 const bool HasUnalignedMemAcc = false; 112}; 113 114using namespace ArmISA; 115 116#endif // __ARCH_ARM_ISA_TRAITS_HH__
| 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Gabe Black 42 * Stephen Hines 43 */ 44 45#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 46#define __ARCH_ARM_ISA_TRAITS_HH__ 47 48#include "arch/arm/types.hh" 49#include "base/types.hh" 50 51namespace LittleEndianGuest {}; 52 53#define TARGET_ARM 54 55class StaticInstPtr; 56 57namespace ArmISA 58{ 59 using namespace LittleEndianGuest; 60 61 StaticInstPtr decodeInst(ExtMachInst); 62 63 // ARM DOES NOT have a delay slot 64 #define ISA_HAS_DELAY_SLOT 0 65 66 const Addr PageShift = 12; 67 const Addr PageBytes = ULL(1) << PageShift; 68 const Addr Page_Mask = ~(PageBytes - 1); 69 const Addr PageOffset = PageBytes - 1; 70 71 72 //////////////////////////////////////////////////////////////////////// 73 // 74 // Translation stuff 75 // 76 77 const Addr PteShift = 3; 78 const Addr NPtePageShift = PageShift - PteShift; 79 const Addr NPtePage = ULL(1) << NPtePageShift; 80 const Addr PteMask = NPtePage - 1; 81 82 //// All 'Mapped' segments go through the TLB 83 //// All other segments are translated by dropping the MSB, to give 84 //// the corresponding physical address 85 // User Segment - Mapped 86 const Addr USegBase = ULL(0x0); 87 const Addr USegEnd = ULL(0x7FFFFFFF); 88 89 // Kernel Segment 0 - Unmapped 90 const Addr KSeg0End = ULL(0x9FFFFFFF); 91 const Addr KSeg0Base = ULL(0x80000000); 92 const Addr KSeg0Mask = ULL(0x1FFFFFFF); 93 94 // For loading... XXX This maybe could be USegEnd?? --ali 95 const Addr LoadAddrMask = ULL(0xffffffffff); 96 97 const unsigned VABits = 32; 98 const unsigned PABits = 32; // Is this correct? 99 const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 100 const Addr VAddrUnImplMask = ~VAddrImplMask; 101 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 102 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 103 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 104 105 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 106 107 // return a no-op instruction... used for instruction fetch faults 108 const ExtMachInst NoopMachInst = 0x00000000; 109 110 const int LogVMPageSize = 12; // 4K bytes 111 const int VMPageSize = (1 << LogVMPageSize); 112 113 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 114 115 const int MachineBytes = 4; 116 const int WordBytes = 4; 117 const int HalfwordBytes = 2; 118 const int ByteBytes = 1; 119 120 const uint32_t HighVecs = 0xFFFF0000; 121 122 // Memory accesses cannot be unaligned 123 const bool HasUnalignedMemAcc = false; 124}; 125 126using namespace ArmISA; 127 128#endif // __ARCH_ARM_ISA_TRAITS_HH__
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