1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_ISA_TRAITS_HH__
34#define __ARCH_ARM_ISA_TRAITS_HH__
35
36#include "arch/arm/types.hh"
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_ISA_TRAITS_HH__
34#define __ARCH_ARM_ISA_TRAITS_HH__
35
36#include "arch/arm/types.hh"
|
38
39namespace LittleEndianGuest {};
40
41#define TARGET_ARM
42
43class StaticInstPtr;
44
45namespace ArmISA
46{
47 using namespace LittleEndianGuest;
48
49 StaticInstPtr decodeInst(ExtMachInst);
50
51 // ARM DOES NOT have a delay slot
52 #define ISA_HAS_DELAY_SLOT 0
53
54 const Addr PageShift = 12;
55 const Addr PageBytes = ULL(1) << PageShift;
56 const Addr Page_Mask = ~(PageBytes - 1);
57 const Addr PageOffset = PageBytes - 1;
58
59
60 ////////////////////////////////////////////////////////////////////////
61 //
62 // Translation stuff
63 //
64
65 const Addr PteShift = 3;
66 const Addr NPtePageShift = PageShift - PteShift;
67 const Addr NPtePage = ULL(1) << NPtePageShift;
68 const Addr PteMask = NPtePage - 1;
69
70 //// All 'Mapped' segments go through the TLB
71 //// All other segments are translated by dropping the MSB, to give
72 //// the corresponding physical address
73 // User Segment - Mapped
74 const Addr USegBase = ULL(0x0);
75 const Addr USegEnd = ULL(0x7FFFFFFF);
76
77 // Kernel Segment 0 - Unmapped
78 const Addr KSeg0End = ULL(0x9FFFFFFF);
79 const Addr KSeg0Base = ULL(0x80000000);
80 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
81
82 // For loading... XXX This maybe could be USegEnd?? --ali
83 const Addr LoadAddrMask = ULL(0xffffffffff);
84
85 const unsigned VABits = 32;
86 const unsigned PABits = 32; // Is this correct?
87 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
88 const Addr VAddrUnImplMask = ~VAddrImplMask;
89 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
90 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
91 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
92
93 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
94
95 // return a no-op instruction... used for instruction fetch faults
96 const ExtMachInst NoopMachInst = 0x00000000;
97
98 // Constants Related to the number of registers
99 const int NumIntArchRegs = 16;
100 const int NumIntSpecialRegs = 19;
101 const int NumFloatArchRegs = 16;
102 const int NumFloatSpecialRegs = 5;
103 const int NumControlRegs = 7;
104 const int NumInternalProcRegs = 0;
105
106 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
107 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
108 const int NumMiscRegs = NumControlRegs;
109
110 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
111
112 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
113
114 // Static instruction parameters
115 const int MaxInstSrcRegs = 5;
116 const int MaxInstDestRegs = 3;
117
118 // semantically meaningful register indices
119 const int ReturnValueReg = 0;
120 const int ReturnValueReg1 = 1;
121 const int ReturnValueReg2 = 2;
122 const int ArgumentReg0 = 0;
123 const int ArgumentReg1 = 1;
124 const int ArgumentReg2 = 2;
125 const int ArgumentReg3 = 3;
126 const int FramePointerReg = 11;
127 const int StackPointerReg = 13;
128 const int ReturnAddressReg = 14;
129 const int PCReg = 15;
130
131 const int ZeroReg = NumIntArchRegs;
132 const int AddrReg = ZeroReg + 1; // Used to generate address for uops
133
134 const int SyscallNumReg = ReturnValueReg;
135 const int SyscallPseudoReturnReg = ReturnValueReg;
136 const int SyscallSuccessReg = ReturnValueReg;
137
138 const int LogVMPageSize = 12; // 4K bytes
139 const int VMPageSize = (1 << LogVMPageSize);
140
141 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
142
143 const int MachineBytes = 4;
144 const int WordBytes = 4;
145 const int HalfwordBytes = 2;
146 const int ByteBytes = 1;
147
148 // These help enumerate all the registers for dependence tracking.
149 const int FP_Base_DepTag = NumIntRegs;
150 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
151};
152
153using namespace ArmISA;
154
155#endif // __ARCH_ARM_ISA_TRAITS_HH__
| 38
39namespace LittleEndianGuest {};
40
41#define TARGET_ARM
42
43class StaticInstPtr;
44
45namespace ArmISA
46{
47 using namespace LittleEndianGuest;
48
49 StaticInstPtr decodeInst(ExtMachInst);
50
51 // ARM DOES NOT have a delay slot
52 #define ISA_HAS_DELAY_SLOT 0
53
54 const Addr PageShift = 12;
55 const Addr PageBytes = ULL(1) << PageShift;
56 const Addr Page_Mask = ~(PageBytes - 1);
57 const Addr PageOffset = PageBytes - 1;
58
59
60 ////////////////////////////////////////////////////////////////////////
61 //
62 // Translation stuff
63 //
64
65 const Addr PteShift = 3;
66 const Addr NPtePageShift = PageShift - PteShift;
67 const Addr NPtePage = ULL(1) << NPtePageShift;
68 const Addr PteMask = NPtePage - 1;
69
70 //// All 'Mapped' segments go through the TLB
71 //// All other segments are translated by dropping the MSB, to give
72 //// the corresponding physical address
73 // User Segment - Mapped
74 const Addr USegBase = ULL(0x0);
75 const Addr USegEnd = ULL(0x7FFFFFFF);
76
77 // Kernel Segment 0 - Unmapped
78 const Addr KSeg0End = ULL(0x9FFFFFFF);
79 const Addr KSeg0Base = ULL(0x80000000);
80 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
81
82 // For loading... XXX This maybe could be USegEnd?? --ali
83 const Addr LoadAddrMask = ULL(0xffffffffff);
84
85 const unsigned VABits = 32;
86 const unsigned PABits = 32; // Is this correct?
87 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
88 const Addr VAddrUnImplMask = ~VAddrImplMask;
89 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
90 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
91 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
92
93 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
94
95 // return a no-op instruction... used for instruction fetch faults
96 const ExtMachInst NoopMachInst = 0x00000000;
97
98 // Constants Related to the number of registers
99 const int NumIntArchRegs = 16;
100 const int NumIntSpecialRegs = 19;
101 const int NumFloatArchRegs = 16;
102 const int NumFloatSpecialRegs = 5;
103 const int NumControlRegs = 7;
104 const int NumInternalProcRegs = 0;
105
106 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
107 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
108 const int NumMiscRegs = NumControlRegs;
109
110 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
111
112 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
113
114 // Static instruction parameters
115 const int MaxInstSrcRegs = 5;
116 const int MaxInstDestRegs = 3;
117
118 // semantically meaningful register indices
119 const int ReturnValueReg = 0;
120 const int ReturnValueReg1 = 1;
121 const int ReturnValueReg2 = 2;
122 const int ArgumentReg0 = 0;
123 const int ArgumentReg1 = 1;
124 const int ArgumentReg2 = 2;
125 const int ArgumentReg3 = 3;
126 const int FramePointerReg = 11;
127 const int StackPointerReg = 13;
128 const int ReturnAddressReg = 14;
129 const int PCReg = 15;
130
131 const int ZeroReg = NumIntArchRegs;
132 const int AddrReg = ZeroReg + 1; // Used to generate address for uops
133
134 const int SyscallNumReg = ReturnValueReg;
135 const int SyscallPseudoReturnReg = ReturnValueReg;
136 const int SyscallSuccessReg = ReturnValueReg;
137
138 const int LogVMPageSize = 12; // 4K bytes
139 const int VMPageSize = (1 << LogVMPageSize);
140
141 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
142
143 const int MachineBytes = 4;
144 const int WordBytes = 4;
145 const int HalfwordBytes = 2;
146 const int ByteBytes = 1;
147
148 // These help enumerate all the registers for dependence tracking.
149 const int FP_Base_DepTag = NumIntRegs;
150 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
151};
152
153using namespace ArmISA;
154
155#endif // __ARCH_ARM_ISA_TRAITS_HH__
|