1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_ISA_DEVICE_HH__
41#define __ARCH_ARM_ISA_DEVICE_HH__
42
43#include "arch/arm/registers.hh"
44#include "base/compiler.hh"
45
46namespace ArmISA
47{
48
| 1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_ISA_DEVICE_HH__
41#define __ARCH_ARM_ISA_DEVICE_HH__
42
43#include "arch/arm/registers.hh"
44#include "base/compiler.hh"
45
46namespace ArmISA
47{
48
|
49/**
50 * Base class for devices that use the MiscReg interfaces.
51 *
52 * This class provides a well-defined interface that the ArmISA class
53 * can use when forwarding MiscReg accesses to a device model (e.g., a
54 * PMU or GIC).
55 */
56class BaseISADevice
57{
58 public:
| 51/**
52 * Base class for devices that use the MiscReg interfaces.
53 *
54 * This class provides a well-defined interface that the ArmISA class
55 * can use when forwarding MiscReg accesses to a device model (e.g., a
56 * PMU or GIC).
57 */
58class BaseISADevice
59{
60 public:
|
62 /**
63 * Write to a system register belonging to this device.
64 *
65 * @param misc_reg Register number (see miscregs.hh)
66 * @param val Value to store
67 */
68 virtual void setMiscReg(int misc_reg, MiscReg val) = 0;
69
70 /**
71 * Read a system register belonging to this device.
72 *
73 * @param misc_reg Register number (see miscregs.hh)
74 * @return Register value.
75 */
76 virtual MiscReg readMiscReg(int misc_reg) = 0;
| 66 /**
67 * Write to a system register belonging to this device.
68 *
69 * @param misc_reg Register number (see miscregs.hh)
70 * @param val Value to store
71 */
72 virtual void setMiscReg(int misc_reg, MiscReg val) = 0;
73
74 /**
75 * Read a system register belonging to this device.
76 *
77 * @param misc_reg Register number (see miscregs.hh)
78 * @return Register value.
79 */
80 virtual MiscReg readMiscReg(int misc_reg) = 0;
|
77};
78
79/**
80 * Dummy device that prints a warning when it is accessed.
81 *
82 * This device can be used as a placeholder when a real device model
83 * is not present. For example, the ISA code uses it to avoid having
84 * to check for a PMU in the register access code.
85 */
86class DummyISADevice : public BaseISADevice
87{
88 public:
89 DummyISADevice()
90 : BaseISADevice() {}
91 ~DummyISADevice() {}
92
93 void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
94 MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
95};
96
97}
98
99#endif // __ARCH_ARM_ISA_DEVICE_HH__
| 84};
85
86/**
87 * Dummy device that prints a warning when it is accessed.
88 *
89 * This device can be used as a placeholder when a real device model
90 * is not present. For example, the ISA code uses it to avoid having
91 * to check for a PMU in the register access code.
92 */
93class DummyISADevice : public BaseISADevice
94{
95 public:
96 DummyISADevice()
97 : BaseISADevice() {}
98 ~DummyISADevice() {}
99
100 void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
101 MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
102};
103
104}
105
106#endif // __ARCH_ARM_ISA_DEVICE_HH__
|