vfp.isa (10037:5cac77888310) vfp.isa (10184:bbfa3152bdea)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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161 %(class_name)s(ExtMachInst machInst,
162 IntRegIndex _dest, IntRegIndex _op1,
163 VfpMicroMode mode = VfpNotAMicroop);
164 %(BasicExecDeclare)s
165};
166}};
167
168def template FpRegRegOpConstructor {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 152 unchanged lines hidden (view full) ---

161 %(class_name)s(ExtMachInst machInst,
162 IntRegIndex _dest, IntRegIndex _op1,
163 VfpMicroMode mode = VfpNotAMicroop);
164 %(BasicExecDeclare)s
165};
166}};
167
168def template FpRegRegOpConstructor {{
169 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
169 %(class_name)s::%(class_name)s(ExtMachInst machInst,
170 IntRegIndex _dest, IntRegIndex _op1,
171 VfpMicroMode mode)
172 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
173 _dest, _op1, mode)
174 {
175 %(constructor)s;
176 if (!(condCode == COND_AL || condCode == COND_UC)) {
177 for (int x = 0; x < _numDestRegs; x++) {

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188 // Constructor
189 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
190 uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
191 %(BasicExecDeclare)s
192};
193}};
194
195def template FpRegImmOpConstructor {{
170 IntRegIndex _dest, IntRegIndex _op1,
171 VfpMicroMode mode)
172 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
173 _dest, _op1, mode)
174 {
175 %(constructor)s;
176 if (!(condCode == COND_AL || condCode == COND_UC)) {
177 for (int x = 0; x < _numDestRegs; x++) {

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188 // Constructor
189 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
190 uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
191 %(BasicExecDeclare)s
192};
193}};
194
195def template FpRegImmOpConstructor {{
196 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
196 %(class_name)s::%(class_name)s(ExtMachInst machInst,
197 IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
198 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
199 _dest, _imm, mode)
200 {
201 %(constructor)s;
202 if (!(condCode == COND_AL || condCode == COND_UC)) {
203 for (int x = 0; x < _numDestRegs; x++) {
204 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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215 %(class_name)s(ExtMachInst machInst,
216 IntRegIndex _dest, IntRegIndex _op1,
217 uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
218 %(BasicExecDeclare)s
219};
220}};
221
222def template FpRegRegImmOpConstructor {{
197 IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
198 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
199 _dest, _imm, mode)
200 {
201 %(constructor)s;
202 if (!(condCode == COND_AL || condCode == COND_UC)) {
203 for (int x = 0; x < _numDestRegs; x++) {
204 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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215 %(class_name)s(ExtMachInst machInst,
216 IntRegIndex _dest, IntRegIndex _op1,
217 uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
218 %(BasicExecDeclare)s
219};
220}};
221
222def template FpRegRegImmOpConstructor {{
223 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
223 %(class_name)s::%(class_name)s(ExtMachInst machInst,
224 IntRegIndex _dest,
225 IntRegIndex _op1,
226 uint64_t _imm,
227 VfpMicroMode mode)
228 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
229 _dest, _op1, _imm, mode)
230 {
231 %(constructor)s;

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245 %(class_name)s(ExtMachInst machInst,
246 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
247 VfpMicroMode mode = VfpNotAMicroop);
248 %(BasicExecDeclare)s
249};
250}};
251
252def template FpRegRegRegOpConstructor {{
224 IntRegIndex _dest,
225 IntRegIndex _op1,
226 uint64_t _imm,
227 VfpMicroMode mode)
228 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
229 _dest, _op1, _imm, mode)
230 {
231 %(constructor)s;

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245 %(class_name)s(ExtMachInst machInst,
246 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
247 VfpMicroMode mode = VfpNotAMicroop);
248 %(BasicExecDeclare)s
249};
250}};
251
252def template FpRegRegRegOpConstructor {{
253 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
253 %(class_name)s::%(class_name)s(ExtMachInst machInst,
254 IntRegIndex _dest,
255 IntRegIndex _op1,
256 IntRegIndex _op2,
257 VfpMicroMode mode)
258 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
259 _dest, _op1, _op2, mode)
260 {
261 %(constructor)s;
262 if (!(condCode == COND_AL || condCode == COND_UC)) {
263 for (int x = 0; x < _numDestRegs; x++) {
264 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
265 }
266 }
267 }
268}};
254 IntRegIndex _dest,
255 IntRegIndex _op1,
256 IntRegIndex _op2,
257 VfpMicroMode mode)
258 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
259 _dest, _op1, _op2, mode)
260 {
261 %(constructor)s;
262 if (!(condCode == COND_AL || condCode == COND_UC)) {
263 for (int x = 0; x < _numDestRegs; x++) {
264 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
265 }
266 }
267 }
268}};