sve_mem.isa (14091:090449e74135) | sve_mem.isa (14106:293e3f4b1321) |
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1// Copyright (c) 2017-2018 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 801 unchanged lines hidden (view full) --- 810 if (fault == NoFault) 811 { 812 %(op_wb)s; 813 } 814 815 return fault; 816 } 817}}; | 1// Copyright (c) 2017-2018 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 801 unchanged lines hidden (view full) --- 810 if (fault == NoFault) 811 { 812 %(op_wb)s; 813 } 814 815 return fault; 816 } 817}}; |
818 819def template SveStructMemSIMicroopDeclare {{ 820 template<class _Element> 821 class %(class_name)s : public %(base_class)s 822 { 823 protected: 824 typedef _Element Element; 825 typedef _Element TPElem; 826 827 IntRegIndex dest; 828 IntRegIndex gp; 829 IntRegIndex base; 830 int64_t imm; 831 832 uint8_t numRegs; 833 int regIndex; 834 835 unsigned memAccessFlags; 836 837 bool baseIsSP; 838 839 public: 840 %(class_name)s(const char* mnem, ExtMachInst machInst, 841 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, 842 int64_t _imm, uint8_t _numRegs, int _regIndex) 843 : %(base_class)s(mnem, machInst, %(op_class)s), 844 dest(_dest), gp(_gp), base(_base), imm(_imm), 845 numRegs(_numRegs), regIndex(_regIndex), 846 memAccessFlags(ArmISA::TLB::AllowUnaligned | 847 ArmISA::TLB::MustBeOne) 848 { 849 %(constructor)s; 850 baseIsSP = isSP(_base); 851 } 852 853 Fault execute(ExecContext *, Trace::InstRecord *) const; 854 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 855 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 856 857 virtual void 858 annotateFault(ArmFault *fault) 859 { 860 %(fa_code)s 861 } 862 863 std::string 864 generateDisassembly(Addr pc, const SymbolTable *symtab) const 865 { 866 std::stringstream ss; 867 printMnemonic(ss, "", false); 868 ccprintf(ss, "{"); 869 switch (dest) { 870 case INTRLVREG0: 871 ccprintf(ss, "INTRLV0"); 872 break; 873 case INTRLVREG1: 874 ccprintf(ss, "INTRLV1"); 875 break; 876 case INTRLVREG2: 877 ccprintf(ss, "INTRLV2"); 878 break; 879 case INTRLVREG3: 880 ccprintf(ss, "INTRLV3"); 881 break; 882 default: 883 printVecReg(ss, dest, true); 884 break; 885 } 886 ccprintf(ss, "}, "); 887 printVecPredReg(ss, gp); 888 if (_opClass == MemReadOp) { 889 ccprintf(ss, "/z"); 890 } 891 ccprintf(ss, ", ["); 892 printVecReg(ss, base, true); 893 if (imm != 0) { 894 ccprintf(ss, ", #%d", imm * sizeof(Element)); 895 } 896 ccprintf(ss, "] (uop reg %d tfer)", regIndex); 897 return ss.str(); 898 } 899 }; 900}}; 901 902def template SveStructMemExecDeclare {{ 903 template 904 Fault %(class_name)s<%(targs)s>::execute(ExecContext *, 905 Trace::InstRecord *) const; 906 907 template 908 Fault %(class_name)s<%(targs)s>::initiateAcc(ExecContext *, 909 Trace::InstRecord *) const; 910 911 template 912 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 913 ExecContext *, Trace::InstRecord *) const; 914}}; 915 916def template SveStructLoadExecute {{ 917 template <class Element> 918 Fault %(class_name)s<Element>::execute(ExecContext *xc, 919 Trace::InstRecord *traceData) const 920 { 921 Addr EA; 922 Fault fault = NoFault; 923 bool aarch64 M5_VAR_USED = true; 924 unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>( 925 xc->tcBase()); 926 927 %(op_decl)s; 928 %(op_rd)s; 929 %(ea_code)s; 930 931 TheISA::VecRegContainer memData; 932 auto memDataView = memData.as<Element>(); 933 934 if (fault == NoFault) { 935 fault = xc->readMem(EA, memData.raw_ptr<uint8_t>(), memAccessSize, 936 this->memAccessFlags); 937 %(memacc_code)s; 938 } 939 940 if (fault == NoFault) { 941 %(op_wb)s; 942 } 943 944 return fault; 945 } 946}}; 947 948def template SveStructLoadInitiateAcc {{ 949 template <class Element> 950 Fault %(class_name)s<Element>::initiateAcc(ExecContext *xc, 951 Trace::InstRecord *traceData) const 952 { 953 Addr EA; 954 Fault fault = NoFault; 955 bool aarch64 M5_VAR_USED = true; 956 unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>( 957 xc->tcBase()); 958 959 %(op_src_decl)s; 960 %(op_rd)s; 961 962 %(ea_code)s; 963 964 if (fault == NoFault) { 965 fault = xc->initiateMemRead(EA, memAccessSize, 966 this->memAccessFlags); 967 } 968 969 return fault; 970 } 971}}; 972 973def template SveStructLoadCompleteAcc {{ 974 template <class Element> 975 Fault %(class_name)s<Element>::completeAcc(PacketPtr pkt, 976 ExecContext *xc, Trace::InstRecord *traceData) const 977 { 978 Fault fault = NoFault; 979 bool aarch64 M5_VAR_USED = true; 980 unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>( 981 xc->tcBase()); 982 983 %(op_decl)s; 984 %(op_rd)s; 985 986 TheISA::VecRegContainer memData; 987 auto memDataView = memData.as<Element>(); 988 989 memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(), 990 pkt->getSize()); 991 992 if (fault == NoFault) { 993 %(memacc_code)s; 994 } 995 996 if (fault == NoFault) { 997 %(op_wb)s; 998 } 999 1000 return fault; 1001 } 1002}}; 1003 1004def template SveStructStoreExecute {{ 1005 template <class Element> 1006 Fault %(class_name)s<Element>::execute(ExecContext *xc, 1007 Trace::InstRecord *traceData) const 1008 { 1009 Addr EA; 1010 Fault fault = NoFault; 1011 bool aarch64 M5_VAR_USED = true; 1012 unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>( 1013 xc->tcBase()); 1014 1015 %(op_decl)s; 1016 %(op_rd)s; 1017 %(ea_code)s; 1018 1019 TheISA::VecRegContainer memData; 1020 auto memDataView = memData.as<Element>(); 1021 1022 %(wren_code)s; 1023 1024 if (fault == NoFault) { 1025 %(memacc_code)s; 1026 } 1027 1028 if (fault == NoFault) { 1029 fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA, 1030 this->memAccessFlags, NULL, wrEn); 1031 } 1032 1033 if (fault == NoFault) { 1034 %(op_wb)s; 1035 } 1036 1037 return fault; 1038 } 1039}}; 1040 1041def template SveStructStoreInitiateAcc {{ 1042 template <class Element> 1043 Fault %(class_name)s<Element>::initiateAcc(ExecContext *xc, 1044 Trace::InstRecord *traceData) const 1045 { 1046 Addr EA; 1047 Fault fault = NoFault; 1048 bool aarch64 M5_VAR_USED = true; 1049 unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>( 1050 xc->tcBase()); 1051 1052 %(op_decl)s; 1053 %(op_rd)s; 1054 %(ea_code)s; 1055 1056 TheISA::VecRegContainer memData; 1057 auto memDataView = memData.as<Element>(); 1058 1059 %(wren_code)s; 1060 1061 if (fault == NoFault) { 1062 %(memacc_code)s; 1063 } 1064 1065 if (fault == NoFault) { 1066 fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA, 1067 this->memAccessFlags, NULL, wrEn); 1068 } 1069 1070 return fault; 1071 } 1072}}; 1073 1074def template SveStructStoreCompleteAcc {{ 1075 template <class Element> 1076 Fault %(class_name)s<Element>::completeAcc(PacketPtr pkt, 1077 ExecContext *xc, Trace::InstRecord *traceData) const 1078 { 1079 return NoFault; 1080 } 1081}}; 1082 1083def template SveStructMemSSMicroopDeclare {{ 1084 template <class _Element> 1085 class %(class_name)s : public %(base_class)s 1086 { 1087 protected: 1088 typedef _Element Element; 1089 typedef _Element TPElem; 1090 1091 IntRegIndex dest; 1092 IntRegIndex gp; 1093 IntRegIndex base; 1094 IntRegIndex offset; 1095 1096 uint8_t numRegs; 1097 int regIndex; 1098 1099 unsigned memAccessFlags; 1100 1101 bool baseIsSP; 1102 1103 public: 1104 %(class_name)s(const char* mnem, ExtMachInst machInst, 1105 IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, 1106 IntRegIndex _offset, uint8_t _numRegs, int _regIndex) 1107 : %(base_class)s(mnem, machInst, %(op_class)s), 1108 dest(_dest), gp(_gp), base(_base), offset(_offset), 1109 numRegs(_numRegs), regIndex(_regIndex), 1110 memAccessFlags(ArmISA::TLB::AllowUnaligned | 1111 ArmISA::TLB::MustBeOne) 1112 { 1113 %(constructor)s; 1114 baseIsSP = isSP(_base); 1115 } 1116 1117 Fault execute(ExecContext *, Trace::InstRecord *) const; 1118 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 1119 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 1120 1121 virtual void 1122 annotateFault(ArmFault *fault) 1123 { 1124 %(fa_code)s 1125 } 1126 1127 std::string 1128 generateDisassembly(Addr pc, const SymbolTable *symtab) const 1129 { 1130 std::stringstream ss; 1131 printMnemonic(ss, "", false); 1132 ccprintf(ss, "{"); 1133 switch (dest) { 1134 case INTRLVREG0: 1135 ccprintf(ss, "INTRLV0"); 1136 break; 1137 case INTRLVREG1: 1138 ccprintf(ss, "INTRLV1"); 1139 break; 1140 case INTRLVREG2: 1141 ccprintf(ss, "INTRLV2"); 1142 break; 1143 case INTRLVREG3: 1144 ccprintf(ss, "INTRLV3"); 1145 break; 1146 default: 1147 printVecReg(ss, dest, true); 1148 break; 1149 } 1150 ccprintf(ss, "}, "); 1151 printVecPredReg(ss, gp); 1152 if (_opClass == MemReadOp) { 1153 ccprintf(ss, "/z"); 1154 } 1155 ccprintf(ss, ", ["); 1156 printIntReg(ss, base); 1157 ccprintf(ss, ", "); 1158 printVecReg(ss, offset, true); 1159 ccprintf(ss, "] (uop reg %d tfer)", regIndex); 1160 return ss.str(); 1161 } 1162 }; 1163}}; 1164 1165def template SveIntrlvMicroopDeclare {{ 1166 template <class _Element> 1167 class %(class_name)s: public %(base_class)s 1168 { 1169 protected: 1170 typedef _Element Element; 1171 typedef _Element TPElem; 1172 IntRegIndex dest; 1173 IntRegIndex op1; 1174 uint8_t numRegs; 1175 int regIndex; 1176 1177 StaticInst *macroOp; 1178 1179 public: 1180 %(class_name)s(const char* mnem, ExtMachInst machInst, 1181 IntRegIndex _dest, IntRegIndex _op1, 1182 uint8_t _numRegs, int _regIndex, StaticInst *_macroOp) 1183 : MicroOp(mnem, machInst, SimdAluOp), 1184 dest(_dest), op1(_op1), numRegs(_numRegs), regIndex(_regIndex), 1185 macroOp(_macroOp) 1186 { 1187 %(constructor)s; 1188 } 1189 1190 Fault execute(ExecContext *, Trace::InstRecord *) const; 1191 1192 std::string 1193 generateDisassembly(Addr pc, const SymbolTable *symtab) const 1194 { 1195 std::stringstream ss; 1196 ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); 1197 ccprintf(ss, " (uop interleave)"); 1198 return ss.str(); 1199 } 1200 }; 1201}}; 1202 1203def template SveDeIntrlvMicroopDeclare {{ 1204 template <class _Element> 1205 class %(class_name)s : public %(base_class)s 1206 { 1207 protected: 1208 typedef _Element Element; 1209 typedef _Element TPElem; 1210 IntRegIndex dest; 1211 uint8_t numRegs; 1212 int regIndex; 1213 1214 StaticInst *macroOp; 1215 1216 public: 1217 %(class_name)s(const char* mnem, ExtMachInst machInst, 1218 IntRegIndex _dest, uint8_t _numRegs, int _regIndex, 1219 StaticInst *_macroOp) 1220 : MicroOp(mnem, machInst, SimdAluOp), 1221 dest(_dest), numRegs(_numRegs), regIndex(_regIndex), 1222 macroOp(_macroOp) 1223 { 1224 %(constructor)s; 1225 } 1226 1227 Fault execute(ExecContext *, Trace::InstRecord *) const; 1228 1229 std::string 1230 generateDisassembly(Addr pc, const SymbolTable *symtab) const 1231 { 1232 std::stringstream ss; 1233 ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); 1234 ccprintf(ss, " (uop deinterleave)"); 1235 return ss.str(); 1236 } 1237 }; 1238}}; 1239 1240def template SveIntrlvMicroopExecDeclare {{ 1241 template 1242 Fault %(class_name)s<%(targs)s>::execute( 1243 ExecContext *, Trace::InstRecord *) const; 1244}}; 1245 1246def template SveIntrlvMicroopExecute {{ 1247 template <class Element> 1248 Fault %(class_name)s<Element>::execute(ExecContext *xc, 1249 Trace::InstRecord *traceData) const 1250 { 1251 Fault fault = NoFault; 1252 %(op_decl)s; 1253 %(op_rd)s; 1254 1255 %(code)s; 1256 if (fault == NoFault) 1257 { 1258 %(op_wb)s; 1259 } 1260 1261 return fault; 1262 } 1263}}; |
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