817a818,1263
>
> def template SveStructMemSIMicroopDeclare {{
> template<class _Element>
> class %(class_name)s : public %(base_class)s
> {
> protected:
> typedef _Element Element;
> typedef _Element TPElem;
>
> IntRegIndex dest;
> IntRegIndex gp;
> IntRegIndex base;
> int64_t imm;
>
> uint8_t numRegs;
> int regIndex;
>
> unsigned memAccessFlags;
>
> bool baseIsSP;
>
> public:
> %(class_name)s(const char* mnem, ExtMachInst machInst,
> IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
> int64_t _imm, uint8_t _numRegs, int _regIndex)
> : %(base_class)s(mnem, machInst, %(op_class)s),
> dest(_dest), gp(_gp), base(_base), imm(_imm),
> numRegs(_numRegs), regIndex(_regIndex),
> memAccessFlags(ArmISA::TLB::AllowUnaligned |
> ArmISA::TLB::MustBeOne)
> {
> %(constructor)s;
> baseIsSP = isSP(_base);
> }
>
> Fault execute(ExecContext *, Trace::InstRecord *) const;
> Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
> Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
>
> virtual void
> annotateFault(ArmFault *fault)
> {
> %(fa_code)s
> }
>
> std::string
> generateDisassembly(Addr pc, const SymbolTable *symtab) const
> {
> std::stringstream ss;
> printMnemonic(ss, "", false);
> ccprintf(ss, "{");
> switch (dest) {
> case INTRLVREG0:
> ccprintf(ss, "INTRLV0");
> break;
> case INTRLVREG1:
> ccprintf(ss, "INTRLV1");
> break;
> case INTRLVREG2:
> ccprintf(ss, "INTRLV2");
> break;
> case INTRLVREG3:
> ccprintf(ss, "INTRLV3");
> break;
> default:
> printVecReg(ss, dest, true);
> break;
> }
> ccprintf(ss, "}, ");
> printVecPredReg(ss, gp);
> if (_opClass == MemReadOp) {
> ccprintf(ss, "/z");
> }
> ccprintf(ss, ", [");
> printVecReg(ss, base, true);
> if (imm != 0) {
> ccprintf(ss, ", #%d", imm * sizeof(Element));
> }
> ccprintf(ss, "] (uop reg %d tfer)", regIndex);
> return ss.str();
> }
> };
> }};
>
> def template SveStructMemExecDeclare {{
> template
> Fault %(class_name)s<%(targs)s>::execute(ExecContext *,
> Trace::InstRecord *) const;
>
> template
> Fault %(class_name)s<%(targs)s>::initiateAcc(ExecContext *,
> Trace::InstRecord *) const;
>
> template
> Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
> ExecContext *, Trace::InstRecord *) const;
> }};
>
> def template SveStructLoadExecute {{
> template <class Element>
> Fault %(class_name)s<Element>::execute(ExecContext *xc,
> Trace::InstRecord *traceData) const
> {
> Addr EA;
> Fault fault = NoFault;
> bool aarch64 M5_VAR_USED = true;
> unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
> xc->tcBase());
>
> %(op_decl)s;
> %(op_rd)s;
> %(ea_code)s;
>
> TheISA::VecRegContainer memData;
> auto memDataView = memData.as<Element>();
>
> if (fault == NoFault) {
> fault = xc->readMem(EA, memData.raw_ptr<uint8_t>(), memAccessSize,
> this->memAccessFlags);
> %(memacc_code)s;
> }
>
> if (fault == NoFault) {
> %(op_wb)s;
> }
>
> return fault;
> }
> }};
>
> def template SveStructLoadInitiateAcc {{
> template <class Element>
> Fault %(class_name)s<Element>::initiateAcc(ExecContext *xc,
> Trace::InstRecord *traceData) const
> {
> Addr EA;
> Fault fault = NoFault;
> bool aarch64 M5_VAR_USED = true;
> unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
> xc->tcBase());
>
> %(op_src_decl)s;
> %(op_rd)s;
>
> %(ea_code)s;
>
> if (fault == NoFault) {
> fault = xc->initiateMemRead(EA, memAccessSize,
> this->memAccessFlags);
> }
>
> return fault;
> }
> }};
>
> def template SveStructLoadCompleteAcc {{
> template <class Element>
> Fault %(class_name)s<Element>::completeAcc(PacketPtr pkt,
> ExecContext *xc, Trace::InstRecord *traceData) const
> {
> Fault fault = NoFault;
> bool aarch64 M5_VAR_USED = true;
> unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
> xc->tcBase());
>
> %(op_decl)s;
> %(op_rd)s;
>
> TheISA::VecRegContainer memData;
> auto memDataView = memData.as<Element>();
>
> memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(),
> pkt->getSize());
>
> if (fault == NoFault) {
> %(memacc_code)s;
> }
>
> if (fault == NoFault) {
> %(op_wb)s;
> }
>
> return fault;
> }
> }};
>
> def template SveStructStoreExecute {{
> template <class Element>
> Fault %(class_name)s<Element>::execute(ExecContext *xc,
> Trace::InstRecord *traceData) const
> {
> Addr EA;
> Fault fault = NoFault;
> bool aarch64 M5_VAR_USED = true;
> unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
> xc->tcBase());
>
> %(op_decl)s;
> %(op_rd)s;
> %(ea_code)s;
>
> TheISA::VecRegContainer memData;
> auto memDataView = memData.as<Element>();
>
> %(wren_code)s;
>
> if (fault == NoFault) {
> %(memacc_code)s;
> }
>
> if (fault == NoFault) {
> fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA,
> this->memAccessFlags, NULL, wrEn);
> }
>
> if (fault == NoFault) {
> %(op_wb)s;
> }
>
> return fault;
> }
> }};
>
> def template SveStructStoreInitiateAcc {{
> template <class Element>
> Fault %(class_name)s<Element>::initiateAcc(ExecContext *xc,
> Trace::InstRecord *traceData) const
> {
> Addr EA;
> Fault fault = NoFault;
> bool aarch64 M5_VAR_USED = true;
> unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
> xc->tcBase());
>
> %(op_decl)s;
> %(op_rd)s;
> %(ea_code)s;
>
> TheISA::VecRegContainer memData;
> auto memDataView = memData.as<Element>();
>
> %(wren_code)s;
>
> if (fault == NoFault) {
> %(memacc_code)s;
> }
>
> if (fault == NoFault) {
> fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA,
> this->memAccessFlags, NULL, wrEn);
> }
>
> return fault;
> }
> }};
>
> def template SveStructStoreCompleteAcc {{
> template <class Element>
> Fault %(class_name)s<Element>::completeAcc(PacketPtr pkt,
> ExecContext *xc, Trace::InstRecord *traceData) const
> {
> return NoFault;
> }
> }};
>
> def template SveStructMemSSMicroopDeclare {{
> template <class _Element>
> class %(class_name)s : public %(base_class)s
> {
> protected:
> typedef _Element Element;
> typedef _Element TPElem;
>
> IntRegIndex dest;
> IntRegIndex gp;
> IntRegIndex base;
> IntRegIndex offset;
>
> uint8_t numRegs;
> int regIndex;
>
> unsigned memAccessFlags;
>
> bool baseIsSP;
>
> public:
> %(class_name)s(const char* mnem, ExtMachInst machInst,
> IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
> IntRegIndex _offset, uint8_t _numRegs, int _regIndex)
> : %(base_class)s(mnem, machInst, %(op_class)s),
> dest(_dest), gp(_gp), base(_base), offset(_offset),
> numRegs(_numRegs), regIndex(_regIndex),
> memAccessFlags(ArmISA::TLB::AllowUnaligned |
> ArmISA::TLB::MustBeOne)
> {
> %(constructor)s;
> baseIsSP = isSP(_base);
> }
>
> Fault execute(ExecContext *, Trace::InstRecord *) const;
> Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
> Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
>
> virtual void
> annotateFault(ArmFault *fault)
> {
> %(fa_code)s
> }
>
> std::string
> generateDisassembly(Addr pc, const SymbolTable *symtab) const
> {
> std::stringstream ss;
> printMnemonic(ss, "", false);
> ccprintf(ss, "{");
> switch (dest) {
> case INTRLVREG0:
> ccprintf(ss, "INTRLV0");
> break;
> case INTRLVREG1:
> ccprintf(ss, "INTRLV1");
> break;
> case INTRLVREG2:
> ccprintf(ss, "INTRLV2");
> break;
> case INTRLVREG3:
> ccprintf(ss, "INTRLV3");
> break;
> default:
> printVecReg(ss, dest, true);
> break;
> }
> ccprintf(ss, "}, ");
> printVecPredReg(ss, gp);
> if (_opClass == MemReadOp) {
> ccprintf(ss, "/z");
> }
> ccprintf(ss, ", [");
> printIntReg(ss, base);
> ccprintf(ss, ", ");
> printVecReg(ss, offset, true);
> ccprintf(ss, "] (uop reg %d tfer)", regIndex);
> return ss.str();
> }
> };
> }};
>
> def template SveIntrlvMicroopDeclare {{
> template <class _Element>
> class %(class_name)s: public %(base_class)s
> {
> protected:
> typedef _Element Element;
> typedef _Element TPElem;
> IntRegIndex dest;
> IntRegIndex op1;
> uint8_t numRegs;
> int regIndex;
>
> StaticInst *macroOp;
>
> public:
> %(class_name)s(const char* mnem, ExtMachInst machInst,
> IntRegIndex _dest, IntRegIndex _op1,
> uint8_t _numRegs, int _regIndex, StaticInst *_macroOp)
> : MicroOp(mnem, machInst, SimdAluOp),
> dest(_dest), op1(_op1), numRegs(_numRegs), regIndex(_regIndex),
> macroOp(_macroOp)
> {
> %(constructor)s;
> }
>
> Fault execute(ExecContext *, Trace::InstRecord *) const;
>
> std::string
> generateDisassembly(Addr pc, const SymbolTable *symtab) const
> {
> std::stringstream ss;
> ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
> ccprintf(ss, " (uop interleave)");
> return ss.str();
> }
> };
> }};
>
> def template SveDeIntrlvMicroopDeclare {{
> template <class _Element>
> class %(class_name)s : public %(base_class)s
> {
> protected:
> typedef _Element Element;
> typedef _Element TPElem;
> IntRegIndex dest;
> uint8_t numRegs;
> int regIndex;
>
> StaticInst *macroOp;
>
> public:
> %(class_name)s(const char* mnem, ExtMachInst machInst,
> IntRegIndex _dest, uint8_t _numRegs, int _regIndex,
> StaticInst *_macroOp)
> : MicroOp(mnem, machInst, SimdAluOp),
> dest(_dest), numRegs(_numRegs), regIndex(_regIndex),
> macroOp(_macroOp)
> {
> %(constructor)s;
> }
>
> Fault execute(ExecContext *, Trace::InstRecord *) const;
>
> std::string
> generateDisassembly(Addr pc, const SymbolTable *symtab) const
> {
> std::stringstream ss;
> ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
> ccprintf(ss, " (uop deinterleave)");
> return ss.str();
> }
> };
> }};
>
> def template SveIntrlvMicroopExecDeclare {{
> template
> Fault %(class_name)s<%(targs)s>::execute(
> ExecContext *, Trace::InstRecord *) const;
> }};
>
> def template SveIntrlvMicroopExecute {{
> template <class Element>
> Fault %(class_name)s<Element>::execute(ExecContext *xc,
> Trace::InstRecord *traceData) const
> {
> Fault fault = NoFault;
> %(op_decl)s;
> %(op_rd)s;
>
> %(code)s;
> if (fault == NoFault)
> {
> %(op_wb)s;
> }
>
> return fault;
> }
> }};