sve_mem.isa (14028:44edf7dbe672) | sve_mem.isa (14091:090449e74135) |
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1// Copyright (c) 2017-2018 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 137 unchanged lines hidden (view full) --- 146 147 %(op_decl)s; 148 %(op_rd)s; 149 %(ea_code)s; 150 151 TheISA::VecRegContainer memData; 152 auto memDataView = memData.as<MemElemType>(); 153 | 1// Copyright (c) 2017-2018 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 137 unchanged lines hidden (view full) --- 146 147 %(op_decl)s; 148 %(op_rd)s; 149 %(ea_code)s; 150 151 TheISA::VecRegContainer memData; 152 auto memDataView = memData.as<MemElemType>(); 153 |
154 if (fault == NoFault) { 155 fault = xc->readMem(EA, memData.raw_ptr<uint8_t>(), memAccessSize, 156 this->memAccessFlags); 157 %(memacc_code)s; 158 } | 154 %(rden_code)s; |
159 | 155 |
156 fault = xc->readMem(EA, memData.raw_ptr<uint8_t>(), memAccessSize, 157 this->memAccessFlags, rdEn); 158 159 %(fault_code)s; 160 |
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160 if (fault == NoFault) { | 161 if (fault == NoFault) { |
162 %(memacc_code)s; |
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161 %(op_wb)s; 162 } 163 164 return fault; 165 } 166}}; 167 168def template SveContigLoadInitiateAcc {{ --- 4 unchanged lines hidden (view full) --- 173 Addr EA; 174 Fault fault = NoFault; 175 bool aarch64 M5_VAR_USED = true; 176 unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( 177 xc->tcBase()); 178 179 %(op_src_decl)s; 180 %(op_rd)s; | 163 %(op_wb)s; 164 } 165 166 return fault; 167 } 168}}; 169 170def template SveContigLoadInitiateAcc {{ --- 4 unchanged lines hidden (view full) --- 175 Addr EA; 176 Fault fault = NoFault; 177 bool aarch64 M5_VAR_USED = true; 178 unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( 179 xc->tcBase()); 180 181 %(op_src_decl)s; 182 %(op_rd)s; |
181 | |
182 %(ea_code)s; 183 | 183 %(ea_code)s; 184 |
184 if (fault == NoFault) { 185 fault = xc->initiateMemRead(EA, memAccessSize, 186 this->memAccessFlags); 187 } | 185 %(rden_code)s; |
188 | 186 |
187 fault = xc->initiateMemRead(EA, memAccessSize, this->memAccessFlags, 188 rdEn); 189 190 %(fault_code)s; 191 |
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189 return fault; 190 } 191}}; 192 193def template SveContigLoadCompleteAcc {{ 194 %(tpl_header)s 195 Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, 196 ExecContext *xc, Trace::InstRecord *traceData) const 197 { | 192 return fault; 193 } 194}}; 195 196def template SveContigLoadCompleteAcc {{ 197 %(tpl_header)s 198 Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, 199 ExecContext *xc, Trace::InstRecord *traceData) const 200 { |
198 Fault fault = NoFault; | |
199 bool aarch64 M5_VAR_USED = true; 200 unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( 201 xc->tcBase()); 202 203 %(op_decl)s; 204 %(op_rd)s; 205 206 TheISA::VecRegContainer memData; 207 auto memDataView = memData.as<MemElemType>(); 208 | 201 bool aarch64 M5_VAR_USED = true; 202 unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( 203 xc->tcBase()); 204 205 %(op_decl)s; 206 %(op_rd)s; 207 208 TheISA::VecRegContainer memData; 209 auto memDataView = memData.as<MemElemType>(); 210 |
209 memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(), 210 pkt->getSize()); 211 212 if (fault == NoFault) { 213 %(memacc_code)s; | 211 if (xc->readMemAccPredicate()) { 212 memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(), 213 pkt->getSize()); |
214 } 215 | 214 } 215 |
216 if (fault == NoFault) { 217 %(op_wb)s; 218 } | 216 %(memacc_code)s; 217 %(op_wb)s; |
219 | 218 |
220 return fault; | 219 return NoFault; |
221 } 222}}; 223 224def template SveContigStoreExecute {{ 225 %(tpl_header)s 226 Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, 227 Trace::InstRecord *traceData) const 228 { --- 164 unchanged lines hidden (view full) --- 393 394 IntRegIndex dest; 395 IntRegIndex gp; 396 IntRegIndex base; 397 uint64_t imm; 398 399 int elemIndex; 400 int numElems; | 220 } 221}}; 222 223def template SveContigStoreExecute {{ 224 %(tpl_header)s 225 Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, 226 Trace::InstRecord *traceData) const 227 { --- 164 unchanged lines hidden (view full) --- 392 393 IntRegIndex dest; 394 IntRegIndex gp; 395 IntRegIndex base; 396 uint64_t imm; 397 398 int elemIndex; 399 int numElems; |
400 bool firstFault; |
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401 402 unsigned memAccessFlags; 403 404 public: 405 %(class_name)s(const char* mnem, ExtMachInst machInst, 406 OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, | 401 402 unsigned memAccessFlags; 403 404 public: 405 %(class_name)s(const char* mnem, ExtMachInst machInst, 406 OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, |
407 IntRegIndex _base, uint64_t _imm, int _elemIndex, int _numElems) | 407 IntRegIndex _base, uint64_t _imm, int _elemIndex, int _numElems, 408 bool _firstFault) |
408 : %(base_class)s(mnem, machInst, %(op_class)s), 409 dest(_dest), gp(_gp), base(_base), imm(_imm), 410 elemIndex(_elemIndex), numElems(_numElems), | 409 : %(base_class)s(mnem, machInst, %(op_class)s), 410 dest(_dest), gp(_gp), base(_base), imm(_imm), 411 elemIndex(_elemIndex), numElems(_numElems), |
412 firstFault(_firstFault), |
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411 memAccessFlags(ArmISA::TLB::AllowUnaligned | 412 ArmISA::TLB::MustBeOne) 413 { 414 %(constructor)s; 415 if (_opClass == MemReadOp && elemIndex == 0) { 416 // The first micro-op is responsible for pinning the | 413 memAccessFlags(ArmISA::TLB::AllowUnaligned | 414 ArmISA::TLB::MustBeOne) 415 { 416 %(constructor)s; 417 if (_opClass == MemReadOp && elemIndex == 0) { 418 // The first micro-op is responsible for pinning the |
417 // destination register 418 _destRegIdx[0].setNumPinnedWrites(numElems - 1); | 419 // destination and the fault status registers 420 assert(_numDestRegs == 2); 421 _destRegIdx[0].setNumPinnedWrites(numElems - 1); 422 _destRegIdx[1].setNumPinnedWrites(numElems - 1); |
419 } 420 } 421 422 Fault execute(ExecContext *, Trace::InstRecord *) const; 423 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 424 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 425 426 virtual void --- 39 unchanged lines hidden (view full) --- 466 IntRegIndex offset; 467 468 bool offsetIs32; 469 bool offsetIsSigned; 470 bool offsetIsScaled; 471 472 int elemIndex; 473 int numElems; | 423 } 424 } 425 426 Fault execute(ExecContext *, Trace::InstRecord *) const; 427 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 428 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 429 430 virtual void --- 39 unchanged lines hidden (view full) --- 470 IntRegIndex offset; 471 472 bool offsetIs32; 473 bool offsetIsSigned; 474 bool offsetIsScaled; 475 476 int elemIndex; 477 int numElems; |
478 bool firstFault; |
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474 475 unsigned memAccessFlags; 476 477 public: 478 %(class_name)s(const char* mnem, ExtMachInst machInst, 479 OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, 480 IntRegIndex _base, IntRegIndex _offset, bool _offsetIs32, 481 bool _offsetIsSigned, bool _offsetIsScaled, int _elemIndex, | 479 480 unsigned memAccessFlags; 481 482 public: 483 %(class_name)s(const char* mnem, ExtMachInst machInst, 484 OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, 485 IntRegIndex _base, IntRegIndex _offset, bool _offsetIs32, 486 bool _offsetIsSigned, bool _offsetIsScaled, int _elemIndex, |
482 int _numElems) | 487 int _numElems, bool _firstFault) |
483 : %(base_class)s(mnem, machInst, %(op_class)s), 484 dest(_dest), gp(_gp), base(_base), offset(_offset), 485 offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned), 486 offsetIsScaled(_offsetIsScaled), elemIndex(_elemIndex), | 488 : %(base_class)s(mnem, machInst, %(op_class)s), 489 dest(_dest), gp(_gp), base(_base), offset(_offset), 490 offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned), 491 offsetIsScaled(_offsetIsScaled), elemIndex(_elemIndex), |
487 numElems(_numElems), | 492 numElems(_numElems), firstFault(_firstFault), |
488 memAccessFlags(ArmISA::TLB::AllowUnaligned | 489 ArmISA::TLB::MustBeOne) 490 { 491 %(constructor)s; 492 if (_opClass == MemReadOp && elemIndex == 0) { 493 // The first micro-op is responsible for pinning the | 493 memAccessFlags(ArmISA::TLB::AllowUnaligned | 494 ArmISA::TLB::MustBeOne) 495 { 496 %(constructor)s; 497 if (_opClass == MemReadOp && elemIndex == 0) { 498 // The first micro-op is responsible for pinning the |
494 // destination register 495 _destRegIdx[0].setNumPinnedWrites(numElems - 1); | 499 // destination and the fault status registers 500 assert(_numDestRegs == 2); 501 _destRegIdx[0].setNumPinnedWrites(numElems - 1); 502 _destRegIdx[1].setNumPinnedWrites(numElems - 1); |
496 } 497 } 498 499 Fault execute(ExecContext *, Trace::InstRecord *) const; 500 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 501 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 502 503 virtual void --- 33 unchanged lines hidden (view full) --- 537 Addr EA; 538 Fault fault = NoFault; 539 bool aarch64 M5_VAR_USED = true; 540 541 %(op_decl)s; 542 %(op_rd)s; 543 %(ea_code)s; 544 | 503 } 504 } 505 506 Fault execute(ExecContext *, Trace::InstRecord *) const; 507 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 508 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 509 510 virtual void --- 33 unchanged lines hidden (view full) --- 544 Addr EA; 545 Fault fault = NoFault; 546 bool aarch64 M5_VAR_USED = true; 547 548 %(op_decl)s; 549 %(op_rd)s; 550 %(ea_code)s; 551 |
545 MemElemType memData; | 552 MemElemType memData = 0; |
546 | 553 |
554 int index = elemIndex; |
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547 if (%(pred_check_code)s) { 548 fault = readMemAtomic(xc, traceData, EA, memData, 549 this->memAccessFlags); 550 } 551 552 if (fault == NoFault) { | 555 if (%(pred_check_code)s) { 556 fault = readMemAtomic(xc, traceData, EA, memData, 557 this->memAccessFlags); 558 } 559 560 if (fault == NoFault) { |
561 %(fault_status_reset_code)s; |
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553 %(memacc_code)s; 554 %(op_wb)s; | 562 %(memacc_code)s; 563 %(op_wb)s; |
555 } | 564 } else { 565 %(fault_status_set_code)s; 566 if (firstFault) { 567 for (index = 0; 568 index < numElems && !(%(pred_check_code)s); 569 index++); |
556 | 570 |
571 if (index < elemIndex) { 572 fault = NoFault; 573 memData = 0; 574 %(memacc_code)s; 575 %(op_wb)s; 576 } 577 } 578 } |
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557 return fault; 558 } 559}}; 560 561def template SveGatherLoadMicroopInitiateAcc {{ 562 %(tpl_header)s 563 Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc, 564 Trace::InstRecord *traceData) const 565 { 566 Addr EA; 567 Fault fault = NoFault; 568 bool aarch64 M5_VAR_USED = true; 569 570 %(op_src_decl)s; 571 %(op_rd)s; 572 %(ea_code)s; 573 574 MemElemType memData; 575 | 579 return fault; 580 } 581}}; 582 583def template SveGatherLoadMicroopInitiateAcc {{ 584 %(tpl_header)s 585 Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc, 586 Trace::InstRecord *traceData) const 587 { 588 Addr EA; 589 Fault fault = NoFault; 590 bool aarch64 M5_VAR_USED = true; 591 592 %(op_src_decl)s; 593 %(op_rd)s; 594 %(ea_code)s; 595 596 MemElemType memData; 597 |
598 int index = elemIndex; |
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576 if (%(pred_check_code)s) { 577 fault = initiateMemRead(xc, traceData, EA, memData, 578 this->memAccessFlags); | 599 if (%(pred_check_code)s) { 600 fault = initiateMemRead(xc, traceData, EA, memData, 601 this->memAccessFlags); |
602 if (fault != NoFault) { 603 %(fault_status_set_code)s; 604 if (firstFault) { 605 for (index = 0; 606 index < numElems && !(%(pred_check_code)s); 607 index++); 608 if (index < elemIndex) { 609 fault = NoFault; 610 xc->setMemAccPredicate(false); 611 } 612 } 613 } else { 614 %(fault_status_reset_code)s; 615 } |
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579 } else { 580 xc->setMemAccPredicate(false); | 616 } else { 617 xc->setMemAccPredicate(false); |
618 %(fault_status_reset_code)s; |
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581 } 582 583 return fault; 584 } 585}}; 586 587def template SveGatherLoadMicroopCompleteAcc {{ 588 %(tpl_header)s 589 Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, 590 ExecContext *xc, Trace::InstRecord *traceData) const 591 { | 619 } 620 621 return fault; 622 } 623}}; 624 625def template SveGatherLoadMicroopCompleteAcc {{ 626 %(tpl_header)s 627 Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, 628 ExecContext *xc, Trace::InstRecord *traceData) const 629 { |
592 Fault fault = NoFault; | |
593 bool aarch64 M5_VAR_USED = true; 594 595 %(op_decl)s; 596 %(op_rd)s; 597 598 MemElemType memData = 0; | 630 bool aarch64 M5_VAR_USED = true; 631 632 %(op_decl)s; 633 %(op_rd)s; 634 635 MemElemType memData = 0; |
599 if (%(pred_check_code)s) { | 636 if (xc->readMemAccPredicate()) { |
600 getMem(pkt, memData, traceData); 601 } 602 | 637 getMem(pkt, memData, traceData); 638 } 639 |
603 if (fault == NoFault) { 604 %(memacc_code)s; 605 } | 640 %(memacc_code)s; 641 %(op_wb)s; |
606 | 642 |
607 if (fault == NoFault) { 608 %(op_wb)s; 609 } 610 611 return fault; | 643 return NoFault; |
612 } 613}}; 614 615def template SveScatterStoreMicroopExecute {{ 616 %(tpl_header)s 617 Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, 618 Trace::InstRecord *traceData) const 619 { 620 Addr EA; 621 Fault fault = NoFault; 622 bool aarch64 M5_VAR_USED = true; 623 624 %(op_decl)s; 625 %(op_rd)s; 626 %(ea_code)s; 627 628 MemElemType memData; 629 %(memacc_code)s; 630 | 644 } 645}}; 646 647def template SveScatterStoreMicroopExecute {{ 648 %(tpl_header)s 649 Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, 650 Trace::InstRecord *traceData) const 651 { 652 Addr EA; 653 Fault fault = NoFault; 654 bool aarch64 M5_VAR_USED = true; 655 656 %(op_decl)s; 657 %(op_rd)s; 658 %(ea_code)s; 659 660 MemElemType memData; 661 %(memacc_code)s; 662 |
663 int index = elemIndex; |
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631 if (%(pred_check_code)s) { 632 fault = writeMemAtomic(xc, traceData, memData, EA, 633 this->memAccessFlags, NULL); 634 } 635 636 if (fault == NoFault) { 637 %(op_wb)s; 638 } --- 13 unchanged lines hidden (view full) --- 652 653 %(op_decl)s; 654 %(op_rd)s; 655 %(ea_code)s; 656 657 MemElemType memData; 658 %(memacc_code)s; 659 | 664 if (%(pred_check_code)s) { 665 fault = writeMemAtomic(xc, traceData, memData, EA, 666 this->memAccessFlags, NULL); 667 } 668 669 if (fault == NoFault) { 670 %(op_wb)s; 671 } --- 13 unchanged lines hidden (view full) --- 685 686 %(op_decl)s; 687 %(op_rd)s; 688 %(ea_code)s; 689 690 MemElemType memData; 691 %(memacc_code)s; 692 |
693 int index = elemIndex; |
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660 if (%(pred_check_code)s) { 661 fault = writeMemTiming(xc, traceData, memData, EA, 662 this->memAccessFlags, NULL); 663 } else { 664 xc->setPredicate(false); 665 } 666 667 return fault; --- 4 unchanged lines hidden (view full) --- 672 %(tpl_header)s 673 Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, 674 ExecContext *xc, Trace::InstRecord *traceData) const 675 { 676 return NoFault; 677 } 678}}; 679 | 694 if (%(pred_check_code)s) { 695 fault = writeMemTiming(xc, traceData, memData, EA, 696 this->memAccessFlags, NULL); 697 } else { 698 xc->setPredicate(false); 699 } 700 701 return fault; --- 4 unchanged lines hidden (view full) --- 706 %(tpl_header)s 707 Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, 708 ExecContext *xc, Trace::InstRecord *traceData) const 709 { 710 return NoFault; 711 } 712}}; 713 |
714def template SveFirstFaultWritebackMicroopDeclare {{ 715 %(tpl_header)s 716 class SveFirstFaultWritebackMicroop : public MicroOp 717 { 718 protected: 719 typedef RegElemType TPElem; 720 721 int numElems; 722 StaticInst *macroOp; 723 724 public: 725 SveFirstFaultWritebackMicroop(const char* mnem, ExtMachInst machInst, 726 OpClass __opClass, int _numElems, StaticInst *_macroOp) 727 : MicroOp(mnem, machInst, __opClass), 728 numElems(_numElems), macroOp(_macroOp) 729 { 730 %(constructor)s; 731 } 732 733 Fault execute(ExecContext *, Trace::InstRecord *) const; 734 735 std::string 736 generateDisassembly(Addr pc, const SymbolTable *symtab) const 737 { 738 std::stringstream ss; 739 ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); 740 ccprintf(ss, " (uop%d)", numElems); 741 return ss.str(); 742 } 743 }; 744}}; 745 746def template SveFirstFaultWritebackMicroopExecute {{ 747 %(tpl_header)s 748 Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, 749 Trace::InstRecord *traceData) const 750 { 751 bool aarch64 M5_VAR_USED = true; 752 753 %(op_decl)s; 754 %(op_rd)s; 755 756 int index, firstFaultIndex; 757 for (index = 0; 758 index < numElems && !%(fault_status_check_code)s; 759 index++); 760 firstFaultIndex = index; 761 for (index = 0; index < numElems; index++) { 762 if (index < firstFaultIndex) { 763 %(first_fault_forward_code)s; 764 } else { 765 %(first_fault_reset_code)s; 766 } 767 } 768 return NoFault; 769 } 770}}; 771 |
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680def template SveGatherLoadCpySrcVecMicroopDeclare {{ 681 class SveGatherLoadCpySrcVecMicroop : public MicroOp 682 { 683 protected: 684 IntRegIndex op1; 685 686 StaticInst *macroOp; 687 --- 38 unchanged lines hidden --- | 772def template SveGatherLoadCpySrcVecMicroopDeclare {{ 773 class SveGatherLoadCpySrcVecMicroop : public MicroOp 774 { 775 protected: 776 IntRegIndex op1; 777 778 StaticInst *macroOp; 779 --- 38 unchanged lines hidden --- |