pred.isa (9250:dab0f29394f0) pred.isa (9573:cac6e95e236c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 63 unchanged lines hidden (view full) ---

72 {
73 %(constructor)s;
74 if (!(condCode == COND_AL || condCode == COND_UC)) {
75 for (int x = 0; x < _numDestRegs; x++) {
76 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
77 }
78 }
79
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 63 unchanged lines hidden (view full) ---

72 {
73 %(constructor)s;
74 if (!(condCode == COND_AL || condCode == COND_UC)) {
75 for (int x = 0; x < _numDestRegs; x++) {
76 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
77 }
78 }
79
80 if (%(is_branch)s){
80 if (%(is_branch)s && !isFloating()){
81 flags[IsControl] = true;
82 flags[IsIndirectControl] = true;
83 if (condCode == COND_AL || condCode == COND_UC)
84 flags[IsUncondControl] = true;
85 else
86 flags[IsCondControl] = true;
87 }
88 }

--- 23 unchanged lines hidden (view full) ---

112 {
113 %(constructor)s;
114 if (!(condCode == COND_AL || condCode == COND_UC)) {
115 for (int x = 0; x < _numDestRegs; x++) {
116 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
117 }
118 }
119
81 flags[IsControl] = true;
82 flags[IsIndirectControl] = true;
83 if (condCode == COND_AL || condCode == COND_UC)
84 flags[IsUncondControl] = true;
85 else
86 flags[IsCondControl] = true;
87 }
88 }

--- 23 unchanged lines hidden (view full) ---

112 {
113 %(constructor)s;
114 if (!(condCode == COND_AL || condCode == COND_UC)) {
115 for (int x = 0; x < _numDestRegs; x++) {
116 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
117 }
118 }
119
120 if (%(is_branch)s){
120 if (%(is_branch)s && !isFloating()){
121 flags[IsControl] = true;
122 flags[IsIndirectControl] = true;
123 if (condCode == COND_AL || condCode == COND_UC)
124 flags[IsUncondControl] = true;
125 else
126 flags[IsCondControl] = true;
127
128 if (%(is_ras_pop)s) {

--- 133 unchanged lines hidden --- 		121 flags[IsControl] = true;
122 flags[IsIndirectControl] = true;
123 if (condCode == COND_AL || condCode == COND_UC)
124 flags[IsUncondControl] = true;
125 else
126 flags[IsCondControl] = true;
127
128 if (%(is_ras_pop)s) {

--- 133 unchanged lines hidden ---