pred.isa (8303:5a95f1d2494e) pred.isa (8518:9c87727099ce)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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200 PseudoInst::quiesceSkip(xc->tcBase());
201#endif
202 }
203
204 return fault;
205 }
206}};
207
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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200 PseudoInst::quiesceSkip(xc->tcBase());
201#endif
202 }
203
204 return fault;
205 }
206}};
207
208def template QuiescePredOpExecuteWithFixup {{
209 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
210 {
211 Fault fault = NoFault;
212 uint64_t resTemp = 0;
213 resTemp = resTemp;
214 %(op_decl)s;
215 %(op_rd)s;
216
217 if (%(predicate_test)s)
218 {
219 %(code)s;
220 if (fault == NoFault)
221 {
222 %(op_wb)s;
223 }
224 } else {
225 xc->setPredicate(false);
226 %(pred_fixup)s;
227#if FULL_SYSTEM
228 PseudoInst::quiesceSkip(xc->tcBase());
229#endif
230 }
231
232 return fault;
233 }
234}};
235
208def template DataDecode {{
209 if (machInst.opcode4 == 0) {
210 if (machInst.sField == 0)
211 return new %(class_name)sImm(machInst);
212 else
213 return new %(class_name)sImmCc(machInst);
214 } else {
215 if (machInst.sField == 0)

--- 12 unchanged lines hidden --- 		236def template DataDecode {{
237 if (machInst.opcode4 == 0) {
238 if (machInst.sField == 0)
239 return new %(class_name)sImm(machInst);
240 else
241 return new %(class_name)sImmCc(machInst);
242 } else {
243 if (machInst.sField == 0)

--- 12 unchanged lines hidden ---