pred.isa (8142:e08035e1a1f6) pred.isa (8203:78b9f056d58a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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102 _dest, _op1, _op2, _shiftAmt, _shiftType)
103 {
104 %(constructor)s;
105 if (!(condCode == COND_AL || condCode == COND_UC)) {
106 for (int x = 0; x < _numDestRegs; x++) {
107 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
108 }
109 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 93 unchanged lines hidden (view full) ---

102 _dest, _op1, _op2, _shiftAmt, _shiftType)
103 {
104 %(constructor)s;
105 if (!(condCode == COND_AL || condCode == COND_UC)) {
106 for (int x = 0; x < _numDestRegs; x++) {
107 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
108 }
109 }
110
111 if (%(is_branch)s){
112 flags[IsControl] = true;
113 flags[IsIndirectControl] = true;
114 if (condCode == COND_AL || condCode == COND_UC)
115 flags[IsCondControl] = true;
116 else
117 flags[IsUncondControl] = true;
118 }
119
120 if (%(is_ras_pop)s) {
121 flags[IsReturn] = true;
122 }
110 }
111}};
112
113def template DataRegRegDeclare {{
114class %(class_name)s : public %(base_class)s
115{
116 public:
117 // Constructor

--- 107 unchanged lines hidden --- 		123 }
124}};
125
126def template DataRegRegDeclare {{
127class %(class_name)s : public %(base_class)s
128{
129 public:
130 // Constructor

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