1// -*- mode:c++ -*- 2 3// Copyright (c) 2010, 2016 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 151 unchanged lines hidden (view full) --- 160 for (int x = 0; x < _numDestRegs; x++) { 161 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 162 } 163 } 164 } 165}}; 166 167def template PredOpExecute {{ |
168 Fault %(class_name)s::execute( 169 ExecContext *xc, Trace::InstRecord *traceData) const |
170 { 171 Fault fault = NoFault; 172 uint64_t resTemp = 0; 173 resTemp = resTemp; 174 %(op_decl)s; 175 %(op_rd)s; 176 177 if (%(predicate_test)s) --- 7 unchanged lines hidden (view full) --- 185 xc->setPredicate(false); 186 } 187 188 return fault; 189 } 190}}; 191 192def template QuiescePredOpExecute {{ |
193 Fault %(class_name)s::execute( 194 ExecContext *xc, Trace::InstRecord *traceData) const |
195 { 196 Fault fault = NoFault; 197 uint64_t resTemp = 0; 198 resTemp = resTemp; 199 %(op_decl)s; 200 %(op_rd)s; 201 202 if (%(predicate_test)s) --- 8 unchanged lines hidden (view full) --- 211 PseudoInst::quiesceSkip(xc->tcBase()); 212 } 213 214 return fault; 215 } 216}}; 217 218def template QuiescePredOpExecuteWithFixup {{ |
219 Fault %(class_name)s::execute( 220 ExecContext *xc, Trace::InstRecord *traceData) const |
221 { 222 Fault fault = NoFault; 223 uint64_t resTemp = 0; 224 resTemp = resTemp; 225 %(op_decl)s; 226 %(op_rd)s; 227 228 if (%(predicate_test)s) --- 36 unchanged lines hidden --- |