pred.isa (9573:cac6e95e236c) | pred.isa (10184:bbfa3152bdea) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 48 unchanged lines hidden (view full) --- 57 // Constructor 58 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 59 IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 60 %(BasicExecDeclare)s 61}; 62}}; 63 64def template DataImmConstructor {{ | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 48 unchanged lines hidden (view full) --- 57 // Constructor 58 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 59 IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 60 %(BasicExecDeclare)s 61}; 62}}; 63 64def template DataImmConstructor {{ |
65 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 65 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
66 IntRegIndex _dest, 67 IntRegIndex _op1, 68 uint32_t _imm, 69 bool _rotC) 70 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 71 _dest, _op1, _imm, _rotC) 72 { 73 %(constructor)s; --- 22 unchanged lines hidden (view full) --- 96 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 97 IntRegIndex _op1, IntRegIndex _op2, 98 int32_t _shiftAmt, ArmShiftType _shiftType); 99 %(BasicExecDeclare)s 100}; 101}}; 102 103def template DataRegConstructor {{ | 66 IntRegIndex _dest, 67 IntRegIndex _op1, 68 uint32_t _imm, 69 bool _rotC) 70 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 71 _dest, _op1, _imm, _rotC) 72 { 73 %(constructor)s; --- 22 unchanged lines hidden (view full) --- 96 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 97 IntRegIndex _op1, IntRegIndex _op2, 98 int32_t _shiftAmt, ArmShiftType _shiftType); 99 %(BasicExecDeclare)s 100}; 101}}; 102 103def template DataRegConstructor {{ |
104 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 104 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
105 IntRegIndex _dest, 106 IntRegIndex _op1, 107 IntRegIndex _op2, 108 int32_t _shiftAmt, 109 ArmShiftType _shiftType) 110 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 111 _dest, _op1, _op2, _shiftAmt, _shiftType) 112 { --- 28 unchanged lines hidden (view full) --- 141 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 142 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 143 ArmShiftType _shiftType); 144 %(BasicExecDeclare)s 145}; 146}}; 147 148def template DataRegRegConstructor {{ | 105 IntRegIndex _dest, 106 IntRegIndex _op1, 107 IntRegIndex _op2, 108 int32_t _shiftAmt, 109 ArmShiftType _shiftType) 110 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 111 _dest, _op1, _op2, _shiftAmt, _shiftType) 112 { --- 28 unchanged lines hidden (view full) --- 141 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 142 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 143 ArmShiftType _shiftType); 144 %(BasicExecDeclare)s 145}; 146}}; 147 148def template DataRegRegConstructor {{ |
149 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 149 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
150 IntRegIndex _dest, 151 IntRegIndex _op1, 152 IntRegIndex _op2, 153 IntRegIndex _shift, 154 ArmShiftType _shiftType) 155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 156 _dest, _op1, _op2, _shift, _shiftType) 157 { --- 104 unchanged lines hidden --- | 150 IntRegIndex _dest, 151 IntRegIndex _op1, 152 IntRegIndex _op2, 153 IntRegIndex _shift, 154 ArmShiftType _shiftType) 155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 156 _dest, _op1, _op2, _shift, _shiftType) 157 { --- 104 unchanged lines hidden --- |