1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Predicated Instruction Execution
46//
47
48let {{
49 predicateTest = 'testPredicate(CondCodes, condCode)'
50}};
51
52def template DataImmDeclare {{
53class %(class_name)s : public %(base_class)s
54{
55 public:
56 // Constructor
57 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
58 IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
59 %(BasicExecDeclare)s
60};
61}};
62
63def template DataImmConstructor {{
64 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
65 IntRegIndex _dest,
66 IntRegIndex _op1,
67 uint32_t _imm,
68 bool _rotC)
69 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
70 _dest, _op1, _imm, _rotC)
71 {
72 %(constructor)s;
73 }
74}};
75
76def template DataRegDeclare {{
77class %(class_name)s : public %(base_class)s
78{
79 public:
80 // Constructor
81 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
82 IntRegIndex _op1, IntRegIndex _op2,
83 int32_t _shiftAmt, ArmShiftType _shiftType);
84 %(BasicExecDeclare)s
85};
86}};
87
88def template DataRegConstructor {{
89 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
90 IntRegIndex _dest,
91 IntRegIndex _op1,
92 IntRegIndex _op2,
93 int32_t _shiftAmt,
94 ArmShiftType _shiftType)
95 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
96 _dest, _op1, _op2, _shiftAmt, _shiftType)
97 {
98 %(constructor)s;
99 }
100}};
101
102def template DataRegRegDeclare {{
103class %(class_name)s : public %(base_class)s
104{
105 public:
106 // Constructor
107 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
108 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
109 ArmShiftType _shiftType);
110 %(BasicExecDeclare)s
111};
112}};
113
114def template DataRegRegConstructor {{
115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
116 IntRegIndex _dest,
117 IntRegIndex _op1,
118 IntRegIndex _op2,
119 IntRegIndex _shift,
120 ArmShiftType _shiftType)
121 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
122 _dest, _op1, _op2, _shift, _shiftType)
123 {
124 %(constructor)s;
125 }
126}};
127
128def template PredOpExecute {{
129 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
130 {
131 Fault fault = NoFault;
132 uint64_t resTemp = 0;
133 resTemp = resTemp;
134 %(op_decl)s;
135 %(op_rd)s;
136
137 if (%(predicate_test)s)
138 {
139 %(code)s;
140 if (fault == NoFault)
141 {
142 %(op_wb)s;
143 }
144 }
145
146 return fault;
147 }
148}};
149
150def template DataDecode {{
151 if (machInst.opcode4 == 0) {
152 if (machInst.sField == 0)
153 return new %(class_name)sImm(machInst);
154 else
155 return new %(class_name)sImmCc(machInst);
156 } else {
157 if (machInst.sField == 0)
158 return new %(class_name)s(machInst);
159 else
160 return new %(class_name)sCc(machInst);
161 }
162}};
163
164def template DataImmDecode {{
165 if (machInst.sField == 0)
166 return new %(class_name)s(machInst);
167 else
168 return new %(class_name)sCc(machInst);
169}};