1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Predicated Instruction Execution
46//
47
48let {{
49 predicateTest = '''
50 testPredicate(CondCodes, machInst.itstateMask ?
51 (ConditionCode)(uint8_t)machInst.itstateCond :
52 condCode)
53 '''
54}};
55
56def template DataImmDeclare {{
57class %(class_name)s : public %(base_class)s
58{
59 public:
60 // Constructor
61 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
62 IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
63 %(BasicExecDeclare)s
64};
65}};
66
67def template DataImmConstructor {{
68 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
69 IntRegIndex _dest,
70 IntRegIndex _op1,
71 uint32_t _imm,
72 bool _rotC)
73 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
74 _dest, _op1, _imm, _rotC)
75 {
76 %(constructor)s;
77 }
78}};
79
80def template DataRegDeclare {{
81class %(class_name)s : public %(base_class)s
82{
83 public:
84 // Constructor
85 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
86 IntRegIndex _op1, IntRegIndex _op2,
87 int32_t _shiftAmt, ArmShiftType _shiftType);
88 %(BasicExecDeclare)s
89};
90}};
91
92def template DataRegConstructor {{
93 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
94 IntRegIndex _dest,
95 IntRegIndex _op1,
96 IntRegIndex _op2,
97 int32_t _shiftAmt,
98 ArmShiftType _shiftType)
99 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
100 _dest, _op1, _op2, _shiftAmt, _shiftType)
101 {
102 %(constructor)s;
103 }
104}};
105
106def template DataRegRegDeclare {{
107class %(class_name)s : public %(base_class)s
108{
109 public:
110 // Constructor
111 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
112 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
113 ArmShiftType _shiftType);
114 %(BasicExecDeclare)s
115};
116}};
117
118def template DataRegRegConstructor {{
119 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
120 IntRegIndex _dest,
121 IntRegIndex _op1,
122 IntRegIndex _op2,
123 IntRegIndex _shift,
124 ArmShiftType _shiftType)
125 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
126 _dest, _op1, _op2, _shift, _shiftType)
127 {
128 %(constructor)s;
129 }
130}};
131
132def template PredOpExecute {{
133 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
134 {
135 Fault fault = NoFault;
136 uint64_t resTemp = 0;
137 resTemp = resTemp;
138 %(op_decl)s;
139 %(op_rd)s;
140
141 if (%(predicate_test)s)
142 {
143 %(code)s;
144 if (fault == NoFault)
145 {
146 %(op_wb)s;
147 }
148 }
149
150 if (fault == NoFault && machInst.itstateMask != 0) {
151 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
152 }
153
154 return fault;
155 }
156}};
157
158def template DataDecode {{
159 if (machInst.opcode4 == 0) {
160 if (machInst.sField == 0)
161 return new %(class_name)sImm(machInst);
162 else
163 return new %(class_name)sImmCc(machInst);
164 } else {
165 if (machInst.sField == 0)
166 return new %(class_name)s(machInst);
167 else
168 return new %(class_name)sCc(machInst);
169 }
170}};
171
172def template DataImmDecode {{
173 if (machInst.sField == 0)
174 return new %(class_name)s(machInst);
175 else
176 return new %(class_name)sCc(machInst);
177}};