1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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66 IntRegIndex _dest,
67 IntRegIndex _op1,
68 uint32_t _imm,
69 bool _rotC)
70 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
71 _dest, _op1, _imm, _rotC)
72 {
73 %(constructor)s;
74 if (!(condCode == COND_AL || condCode == COND_UC)) {
75 for (int x = 0; x < _numDestRegs; x++) {
76 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
77 }
78 }
79 }
80}};
81
82def template DataRegDeclare {{
83class %(class_name)s : public %(base_class)s
84{
85 public:
86 // Constructor

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97 IntRegIndex _op1,
98 IntRegIndex _op2,
99 int32_t _shiftAmt,
100 ArmShiftType _shiftType)
101 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
102 _dest, _op1, _op2, _shiftAmt, _shiftType)
103 {
104 %(constructor)s;
105 if (!(condCode == COND_AL || condCode == COND_UC)) {
106 for (int x = 0; x < _numDestRegs; x++) {
107 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
108 }
109 }
110 }
111}};
112
113def template DataRegRegDeclare {{
114class %(class_name)s : public %(base_class)s
115{
116 public:
117 // Constructor

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128 IntRegIndex _op1,
129 IntRegIndex _op2,
130 IntRegIndex _shift,
131 ArmShiftType _shiftType)
132 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
133 _dest, _op1, _op2, _shift, _shiftType)
134 {
135 %(constructor)s;
136 if (!(condCode == COND_AL || condCode == COND_UC)) {
137 for (int x = 0; x < _numDestRegs; x++) {
138 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
139 }
140 }
141 }
142}};
143
144def template PredOpExecute {{
145 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
146 {
147 Fault fault = NoFault;
148 uint64_t resTemp = 0;

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