1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41 simdEnabledCheckCode = '''
42 {
43 Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
44 Cpsr, Cpacr, Nsacr, Fpexc,
45 true, true);
46 if (fault != NoFault)
47 return fault;
48 }
49 '''
50}};
51
52
53def template NeonRegRegRegOpDeclare {{
54template <class _Element>
55class %(class_name)s : public %(base_class)s
56{
57 protected:
58 typedef _Element Element;
59 public:
60 // Constructor
61 %(class_name)s(ExtMachInst machInst,
62 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
63 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
64 _dest, _op1, _op2)
65 {
66 %(constructor)s;
67 if (!(condCode == COND_AL || condCode == COND_UC)) {
68 for (int x = 0; x < _numDestRegs; x++) {
69 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
70 }
71 }
72 }
73
74 Fault execute(ExecContext *, Trace::InstRecord *) const override;
75};
76}};
77
78def template NeonRegRegRegImmOpDeclare {{
79template <class _Element>
80class %(class_name)s : public %(base_class)s
81{
82 protected:
83 typedef _Element Element;
84 public:
85 // Constructor
86 %(class_name)s(ExtMachInst machInst,
87 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
88 uint64_t _imm)
89 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
90 _dest, _op1, _op2, _imm)
91 {
92 %(constructor)s;
93 if (!(condCode == COND_AL || condCode == COND_UC)) {
94 for (int x = 0; x < _numDestRegs; x++) {
95 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
96 }
97 }
98 }
99
100 Fault execute(ExecContext *, Trace::InstRecord *) const override;
101};
102}};
103
104def template NeonRegRegImmOpDeclare {{
105template <class _Element>
106class %(class_name)s : public %(base_class)s
107{
108 protected:
109 typedef _Element Element;
110 public:
111 // Constructor
112 %(class_name)s(ExtMachInst machInst,
113 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
114 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
115 _dest, _op1, _imm)
116 {
117 %(constructor)s;
118 if (!(condCode == COND_AL || condCode == COND_UC)) {
119 for (int x = 0; x < _numDestRegs; x++) {
120 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
121 }
122 }
123 }
124
125 Fault execute(ExecContext *, Trace::InstRecord *) const override;
126};
127}};
128
129def template NeonRegImmOpDeclare {{
130template <class _Element>
131class %(class_name)s : public %(base_class)s
132{
133 protected:
134 typedef _Element Element;
135 public:
136 // Constructor
137 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm)
138 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
139 {
140 %(constructor)s;
141 if (!(condCode == COND_AL || condCode == COND_UC)) {
142 for (int x = 0; x < _numDestRegs; x++) {
143 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
144 }
145 }
146 }
147
148 Fault execute(ExecContext *, Trace::InstRecord *) const override;
149};
150}};
151
152def template NeonRegRegOpDeclare {{
153template <class _Element>
154class %(class_name)s : public %(base_class)s
155{
156 protected:
157 typedef _Element Element;
158 public:
159 // Constructor
160 %(class_name)s(ExtMachInst machInst,
161 IntRegIndex _dest, IntRegIndex _op1)
162 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
163 _dest, _op1)
164 {
165 %(constructor)s;
166 if (!(condCode == COND_AL || condCode == COND_UC)) {
167 for (int x = 0; x < _numDestRegs; x++) {
168 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
169 }
170 }
171 }
172
173 Fault execute(ExecContext *, Trace::InstRecord *) const override;
174};
175}};
176
177def template NeonExecDeclare {{
178 template
179 Fault %(class_name)s<%(targs)s>::execute(
180 ExecContext *, Trace::InstRecord *) const;
181}};
182
183output header {{
184 template <class T>
185 // Implement a less-than-zero function: ltz()
186 // this function exists because some versions of GCC complain when a
187 // comparison is done between a unsigned variable and 0 and for GCC 4.2
188 // there is no way to disable this warning
189 inline bool ltz(T t);
190
191 template <>
192 inline bool ltz(uint8_t) { return false; }
193 template <>
194 inline bool ltz(uint16_t) { return false; }
195 template <>
196 inline bool ltz(uint32_t) { return false; }
197 template <>
198 inline bool ltz(uint64_t) { return false; }
199 template <>
200 inline bool ltz(int8_t v) { return v < 0; }
201 template <>
202 inline bool ltz(int16_t v) { return v < 0; }
203 template <>
204 inline bool ltz(int32_t v) { return v < 0; }
205 template <>
206 inline bool ltz(int64_t v) { return v < 0; }
207}};
208
209def template NeonEqualRegExecute {{
210 template <class Element>
211 Fault %(class_name)s<Element>::execute(ExecContext *xc,
212 Trace::InstRecord *traceData) const
213 {
214 Fault fault = NoFault;
215 %(op_decl)s;
216 %(op_rd)s;
217
218 const unsigned rCount = %(r_count)d;
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41 simdEnabledCheckCode = '''
42 {
43 Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
44 Cpsr, Cpacr, Nsacr, Fpexc,
45 true, true);
46 if (fault != NoFault)
47 return fault;
48 }
49 '''
50}};
51
52
53def template NeonRegRegRegOpDeclare {{
54template <class _Element>
55class %(class_name)s : public %(base_class)s
56{
57 protected:
58 typedef _Element Element;
59 public:
60 // Constructor
61 %(class_name)s(ExtMachInst machInst,
62 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
63 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
64 _dest, _op1, _op2)
65 {
66 %(constructor)s;
67 if (!(condCode == COND_AL || condCode == COND_UC)) {
68 for (int x = 0; x < _numDestRegs; x++) {
69 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
70 }
71 }
72 }
73
74 Fault execute(ExecContext *, Trace::InstRecord *) const override;
75};
76}};
77
78def template NeonRegRegRegImmOpDeclare {{
79template <class _Element>
80class %(class_name)s : public %(base_class)s
81{
82 protected:
83 typedef _Element Element;
84 public:
85 // Constructor
86 %(class_name)s(ExtMachInst machInst,
87 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
88 uint64_t _imm)
89 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
90 _dest, _op1, _op2, _imm)
91 {
92 %(constructor)s;
93 if (!(condCode == COND_AL || condCode == COND_UC)) {
94 for (int x = 0; x < _numDestRegs; x++) {
95 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
96 }
97 }
98 }
99
100 Fault execute(ExecContext *, Trace::InstRecord *) const override;
101};
102}};
103
104def template NeonRegRegImmOpDeclare {{
105template <class _Element>
106class %(class_name)s : public %(base_class)s
107{
108 protected:
109 typedef _Element Element;
110 public:
111 // Constructor
112 %(class_name)s(ExtMachInst machInst,
113 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
114 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
115 _dest, _op1, _imm)
116 {
117 %(constructor)s;
118 if (!(condCode == COND_AL || condCode == COND_UC)) {
119 for (int x = 0; x < _numDestRegs; x++) {
120 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
121 }
122 }
123 }
124
125 Fault execute(ExecContext *, Trace::InstRecord *) const override;
126};
127}};
128
129def template NeonRegImmOpDeclare {{
130template <class _Element>
131class %(class_name)s : public %(base_class)s
132{
133 protected:
134 typedef _Element Element;
135 public:
136 // Constructor
137 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm)
138 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
139 {
140 %(constructor)s;
141 if (!(condCode == COND_AL || condCode == COND_UC)) {
142 for (int x = 0; x < _numDestRegs; x++) {
143 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
144 }
145 }
146 }
147
148 Fault execute(ExecContext *, Trace::InstRecord *) const override;
149};
150}};
151
152def template NeonRegRegOpDeclare {{
153template <class _Element>
154class %(class_name)s : public %(base_class)s
155{
156 protected:
157 typedef _Element Element;
158 public:
159 // Constructor
160 %(class_name)s(ExtMachInst machInst,
161 IntRegIndex _dest, IntRegIndex _op1)
162 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
163 _dest, _op1)
164 {
165 %(constructor)s;
166 if (!(condCode == COND_AL || condCode == COND_UC)) {
167 for (int x = 0; x < _numDestRegs; x++) {
168 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
169 }
170 }
171 }
172
173 Fault execute(ExecContext *, Trace::InstRecord *) const override;
174};
175}};
176
177def template NeonExecDeclare {{
178 template
179 Fault %(class_name)s<%(targs)s>::execute(
180 ExecContext *, Trace::InstRecord *) const;
181}};
182
183output header {{
184 template <class T>
185 // Implement a less-than-zero function: ltz()
186 // this function exists because some versions of GCC complain when a
187 // comparison is done between a unsigned variable and 0 and for GCC 4.2
188 // there is no way to disable this warning
189 inline bool ltz(T t);
190
191 template <>
192 inline bool ltz(uint8_t) { return false; }
193 template <>
194 inline bool ltz(uint16_t) { return false; }
195 template <>
196 inline bool ltz(uint32_t) { return false; }
197 template <>
198 inline bool ltz(uint64_t) { return false; }
199 template <>
200 inline bool ltz(int8_t v) { return v < 0; }
201 template <>
202 inline bool ltz(int16_t v) { return v < 0; }
203 template <>
204 inline bool ltz(int32_t v) { return v < 0; }
205 template <>
206 inline bool ltz(int64_t v) { return v < 0; }
207}};
208
209def template NeonEqualRegExecute {{
210 template <class Element>
211 Fault %(class_name)s<Element>::execute(ExecContext *xc,
212 Trace::InstRecord *traceData) const
213 {
214 Fault fault = NoFault;
215 %(op_decl)s;
216 %(op_rd)s;
217
218 const unsigned rCount = %(r_count)d;
|