1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2012 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 simdEnabledCheckCode = ''' 42 { 43 uint32_t issEnCheck; 44 bool trapEnCheck; 45 uint32_t seq; 46 if (!vfpNeonEnabled(seq, Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck, 47 trapEnCheck, xc->tcBase(), Fpexc, true)) 48 {return disabledFault();} 49 if (trapEnCheck) { 50 CPSR cpsrEnCheck = Cpsr; 51 if (cpsrEnCheck.mode == MODE_HYP) { 52 return new UndefinedInstruction(machInst, issEnCheck, 53 EC_TRAPPED_HCPTR); 54 } else { 55 if (!inSecureState(Scr, Cpsr)) { 56 return new HypervisorTrap(machInst, issEnCheck, 57 EC_TRAPPED_HCPTR); 58 } 59 } 60 } 61 } 62 ''' 63}}; 64 65 66def template NeonRegRegRegOpDeclare {{ 67template <class _Element> 68class %(class_name)s : public %(base_class)s 69{ 70 protected: 71 typedef _Element Element; 72 public: 73 // Constructor 74 %(class_name)s(ExtMachInst machInst, 75 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) 76 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 77 _dest, _op1, _op2) 78 { 79 %(constructor)s; 80 if (!(condCode == COND_AL || condCode == COND_UC)) { 81 for (int x = 0; x < _numDestRegs; x++) { 82 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 83 } 84 } 85 } 86 87 %(BasicExecDeclare)s 88}; 89}}; 90 91def template NeonRegRegRegImmOpDeclare {{ 92template <class _Element> 93class %(class_name)s : public %(base_class)s 94{ 95 protected: 96 typedef _Element Element; 97 public: 98 // Constructor 99 %(class_name)s(ExtMachInst machInst, 100 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 101 uint64_t _imm) 102 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 103 _dest, _op1, _op2, _imm) 104 { 105 %(constructor)s; 106 if (!(condCode == COND_AL || condCode == COND_UC)) { 107 for (int x = 0; x < _numDestRegs; x++) { 108 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 109 } 110 } 111 } 112 113 %(BasicExecDeclare)s 114}; 115}}; 116 117def template NeonRegRegImmOpDeclare {{ 118template <class _Element> 119class %(class_name)s : public %(base_class)s 120{ 121 protected: 122 typedef _Element Element; 123 public: 124 // Constructor 125 %(class_name)s(ExtMachInst machInst, 126 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) 127 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 128 _dest, _op1, _imm) 129 { 130 %(constructor)s; 131 if (!(condCode == COND_AL || condCode == COND_UC)) { 132 for (int x = 0; x < _numDestRegs; x++) { 133 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 134 } 135 } 136 } 137 138 %(BasicExecDeclare)s 139}; 140}}; 141 142def template NeonRegImmOpDeclare {{ 143template <class _Element> 144class %(class_name)s : public %(base_class)s 145{ 146 protected: 147 typedef _Element Element; 148 public: 149 // Constructor 150 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) 151 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) 152 { 153 %(constructor)s; 154 if (!(condCode == COND_AL || condCode == COND_UC)) { 155 for (int x = 0; x < _numDestRegs; x++) { 156 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 157 } 158 } 159 } 160 161 %(BasicExecDeclare)s 162}; 163}}; 164 165def template NeonRegRegOpDeclare {{ 166template <class _Element> 167class %(class_name)s : public %(base_class)s 168{ 169 protected: 170 typedef _Element Element; 171 public: 172 // Constructor 173 %(class_name)s(ExtMachInst machInst, 174 IntRegIndex _dest, IntRegIndex _op1) 175 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 176 _dest, _op1) 177 { 178 %(constructor)s; 179 if (!(condCode == COND_AL || condCode == COND_UC)) { 180 for (int x = 0; x < _numDestRegs; x++) { 181 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 182 } 183 } 184 } 185 186 %(BasicExecDeclare)s 187}; 188}}; 189 190def template NeonExecDeclare {{ 191 template 192 Fault %(class_name)s<%(targs)s>::execute(
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2012 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 simdEnabledCheckCode = ''' 42 { 43 uint32_t issEnCheck; 44 bool trapEnCheck; 45 uint32_t seq; 46 if (!vfpNeonEnabled(seq, Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck, 47 trapEnCheck, xc->tcBase(), Fpexc, true)) 48 {return disabledFault();} 49 if (trapEnCheck) { 50 CPSR cpsrEnCheck = Cpsr; 51 if (cpsrEnCheck.mode == MODE_HYP) { 52 return new UndefinedInstruction(machInst, issEnCheck, 53 EC_TRAPPED_HCPTR); 54 } else { 55 if (!inSecureState(Scr, Cpsr)) { 56 return new HypervisorTrap(machInst, issEnCheck, 57 EC_TRAPPED_HCPTR); 58 } 59 } 60 } 61 } 62 ''' 63}}; 64 65 66def template NeonRegRegRegOpDeclare {{ 67template <class _Element> 68class %(class_name)s : public %(base_class)s 69{ 70 protected: 71 typedef _Element Element; 72 public: 73 // Constructor 74 %(class_name)s(ExtMachInst machInst, 75 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) 76 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 77 _dest, _op1, _op2) 78 { 79 %(constructor)s; 80 if (!(condCode == COND_AL || condCode == COND_UC)) { 81 for (int x = 0; x < _numDestRegs; x++) { 82 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 83 } 84 } 85 } 86 87 %(BasicExecDeclare)s 88}; 89}}; 90 91def template NeonRegRegRegImmOpDeclare {{ 92template <class _Element> 93class %(class_name)s : public %(base_class)s 94{ 95 protected: 96 typedef _Element Element; 97 public: 98 // Constructor 99 %(class_name)s(ExtMachInst machInst, 100 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 101 uint64_t _imm) 102 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 103 _dest, _op1, _op2, _imm) 104 { 105 %(constructor)s; 106 if (!(condCode == COND_AL || condCode == COND_UC)) { 107 for (int x = 0; x < _numDestRegs; x++) { 108 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 109 } 110 } 111 } 112 113 %(BasicExecDeclare)s 114}; 115}}; 116 117def template NeonRegRegImmOpDeclare {{ 118template <class _Element> 119class %(class_name)s : public %(base_class)s 120{ 121 protected: 122 typedef _Element Element; 123 public: 124 // Constructor 125 %(class_name)s(ExtMachInst machInst, 126 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) 127 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 128 _dest, _op1, _imm) 129 { 130 %(constructor)s; 131 if (!(condCode == COND_AL || condCode == COND_UC)) { 132 for (int x = 0; x < _numDestRegs; x++) { 133 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 134 } 135 } 136 } 137 138 %(BasicExecDeclare)s 139}; 140}}; 141 142def template NeonRegImmOpDeclare {{ 143template <class _Element> 144class %(class_name)s : public %(base_class)s 145{ 146 protected: 147 typedef _Element Element; 148 public: 149 // Constructor 150 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) 151 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) 152 { 153 %(constructor)s; 154 if (!(condCode == COND_AL || condCode == COND_UC)) { 155 for (int x = 0; x < _numDestRegs; x++) { 156 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 157 } 158 } 159 } 160 161 %(BasicExecDeclare)s 162}; 163}}; 164 165def template NeonRegRegOpDeclare {{ 166template <class _Element> 167class %(class_name)s : public %(base_class)s 168{ 169 protected: 170 typedef _Element Element; 171 public: 172 // Constructor 173 %(class_name)s(ExtMachInst machInst, 174 IntRegIndex _dest, IntRegIndex _op1) 175 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 176 _dest, _op1) 177 { 178 %(constructor)s; 179 if (!(condCode == COND_AL || condCode == COND_UC)) { 180 for (int x = 0; x < _numDestRegs; x++) { 181 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 182 } 183 } 184 } 185 186 %(BasicExecDeclare)s 187}; 188}}; 189 190def template NeonExecDeclare {{ 191 template 192 Fault %(class_name)s<%(targs)s>::execute(
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