misc.isa (8205:7ecbffb674aa) misc.isa (8209:9e3f7f00fa90)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 388 unchanged lines hidden (view full) ---

397 if (!(condCode == COND_AL || condCode == COND_UC)) {
398 for (int x = 0; x < _numDestRegs; x++) {
399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
400 }
401 }
402 }
403}};
404
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 388 unchanged lines hidden (view full) ---

397 if (!(condCode == COND_AL || condCode == COND_UC)) {
398 for (int x = 0; x < _numDestRegs; x++) {
399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
400 }
401 }
402 }
403}};
404
405def template ClrexDeclare {{
406 /**
407 * Static instruction class for "%(mnemonic)s".
408 */
409 class %(class_name)s : public %(base_class)s
410 {
411 public:
412
413 /// Constructor.
414 %(class_name)s(ExtMachInst machInst);
415
416 %(BasicExecDeclare)s
417
418 %(InitiateAccDeclare)s
419
420 %(CompleteAccDeclare)s
421 };
422}};
423
424def template ClrexInitiateAcc {{
425 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
426 Trace::InstRecord *traceData) const
427 {
428 Fault fault = NoFault;
429 %(op_decl)s;
430 %(op_rd)s;
431
432 if (%(predicate_test)s)
433 {
434 if (fault == NoFault) {
435 unsigned memAccessFlags = Request::CLEAR_LL |
436 ArmISA::TLB::AlignWord | Request::LLSC;
437 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
438 }
439 } else {
440 xc->setPredicate(false);
441 }
442
443 return fault;
444 }
445}};
446
447def template ClrexCompleteAcc {{
448 Fault %(class_name)s::completeAcc(PacketPtr pkt,
449 %(CPU_exec_context)s *xc,
450 Trace::InstRecord *traceData) const
451 {
452 return NoFault;
453 }
454}};
455