misc.isa (7848:cc5e64f8423f) misc.isa (8205:7ecbffb674aa)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 424 unchanged lines hidden (view full) ---

433 {
434 if (fault == NoFault) {
435 unsigned memAccessFlags = Request::CLEAR_LL |
436 ArmISA::TLB::AlignWord | Request::LLSC;
437 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
438 }
439 } else {
440 xc->setPredicate(false);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 424 unchanged lines hidden (view full) ---

433 {
434 if (fault == NoFault) {
435 unsigned memAccessFlags = Request::CLEAR_LL |
436 ArmISA::TLB::AlignWord | Request::LLSC;
437 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
438 }
439 } else {
440 xc->setPredicate(false);
441 if (fault == NoFault && machInst.itstateMask != 0) {
442 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
443 }
444 }
445
446 return fault;
447 }
448}};
449
450def template ClrexCompleteAcc {{
451 Fault %(class_name)s::completeAcc(PacketPtr pkt,
452 %(CPU_exec_context)s *xc,
453 Trace::InstRecord *traceData) const
454 {
441 }
442
443 return fault;
444 }
445}};
446
447def template ClrexCompleteAcc {{
448 Fault %(class_name)s::completeAcc(PacketPtr pkt,
449 %(CPU_exec_context)s *xc,
450 Trace::InstRecord *traceData) const
451 {
455 if (machInst.itstateMask != 0) {
456 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
457 }
458
459 return NoFault;
460 }
461}};
462
452 return NoFault;
453 }
454}};
455