misc.isa (7705:fd65f85fcc0c) misc.isa (7712:7733c562e5e3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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382 }
383}};
384
385def template ClrexCompleteAcc {{
386 Fault %(class_name)s::completeAcc(PacketPtr pkt,
387 %(CPU_exec_context)s *xc,
388 Trace::InstRecord *traceData) const
389 {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 373 unchanged lines hidden (view full) ---

382 }
383}};
384
385def template ClrexCompleteAcc {{
386 Fault %(class_name)s::completeAcc(PacketPtr pkt,
387 %(CPU_exec_context)s *xc,
388 Trace::InstRecord *traceData) const
389 {
390 Fault fault = NoFault;
391
392 %(op_decl)s;
393 %(op_rd)s;
394
395
396 if (fault == NoFault && machInst.itstateMask != 0) {
390 if (machInst.itstateMask != 0) {
397 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
398 }
399
391 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
392 }
393
400 return fault;
394 return NoFault;
401 }
402}};
403
395 }
396}};
397