misc.isa (7609:70e5fb74b4fa) misc.isa (7612:917946898102)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 353 unchanged lines hidden (view full) ---

362 {
363 Fault fault = NoFault;
364 %(op_decl)s;
365 %(op_rd)s;
366
367 if (%(predicate_test)s)
368 {
369 if (fault == NoFault) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 353 unchanged lines hidden (view full) ---

362 {
363 Fault fault = NoFault;
364 %(op_decl)s;
365 %(op_rd)s;
366
367 if (%(predicate_test)s)
368 {
369 if (fault == NoFault) {
370 unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
370 unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
371 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
372 }
373 } else {
374 xc->setPredicate(false);
375 if (fault == NoFault && machInst.itstateMask != 0) {
376 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
377 }
378 }

--- 24 unchanged lines hidden --- 		371 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
372 }
373 } else {
374 xc->setPredicate(false);
375 if (fault == NoFault && machInst.itstateMask != 0) {
376 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
377 }
378 }

--- 24 unchanged lines hidden ---