misc.isa (7332:2e611548bb5a) misc.isa (7609:70e5fb74b4fa)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 322 unchanged lines hidden (view full) ---

331 int32_t _shiftAmt,
332 ArmShiftType _shiftType)
333 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
334 _dest, _imm, _op1, _shiftAmt, _shiftType)
335 {
336 %(constructor)s;
337 }
338}};
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 322 unchanged lines hidden (view full) ---

331 int32_t _shiftAmt,
332 ArmShiftType _shiftType)
333 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
334 _dest, _imm, _op1, _shiftAmt, _shiftType)
335 {
336 %(constructor)s;
337 }
338}};
339
340def template ClrexDeclare {{
341 /**
342 * Static instruction class for "%(mnemonic)s".
343 */
344 class %(class_name)s : public %(base_class)s
345 {
346 public:
347
348 /// Constructor.
349 %(class_name)s(ExtMachInst machInst);
350
351 %(BasicExecDeclare)s
352
353 %(InitiateAccDeclare)s
354
355 %(CompleteAccDeclare)s
356 };
357}};
358
359def template ClrexInitiateAcc {{
360 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
361 Trace::InstRecord *traceData) const
362 {
363 Fault fault = NoFault;
364 %(op_decl)s;
365 %(op_rd)s;
366
367 if (%(predicate_test)s)
368 {
369 if (fault == NoFault) {
370 unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
371 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
372 }
373 } else {
374 xc->setPredicate(false);
375 if (fault == NoFault && machInst.itstateMask != 0) {
376 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
377 }
378 }
379
380 return fault;
381 }
382}};
383
384def template ClrexCompleteAcc {{
385 Fault %(class_name)s::completeAcc(PacketPtr pkt,
386 %(CPU_exec_context)s *xc,
387 Trace::InstRecord *traceData) const
388 {
389 Fault fault = NoFault;
390
391 %(op_decl)s;
392 %(op_rd)s;
393
394
395 if (fault == NoFault && machInst.itstateMask != 0) {
396 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
397 }
398
399 return fault;
400 }
401}};
402