misc.isa (7225:bf41a07cc7c0) misc.isa (7232:f633e1a3f644)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 106 unchanged lines hidden (view full) ---

115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
116 IntRegIndex _dest, IntRegIndex _op1)
117 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
118 {
119 %(constructor)s;
120 }
121}};
122
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 106 unchanged lines hidden (view full) ---

115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
116 IntRegIndex _dest, IntRegIndex _op1)
117 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
118 {
119 %(constructor)s;
120 }
121}};
122
123def template SatOpDeclare {{
123def template RegImmRegOpDeclare {{
124class %(class_name)s : public %(base_class)s
125{
126 protected:
127 public:
128 // Constructor
129 %(class_name)s(ExtMachInst machInst,
124class %(class_name)s : public %(base_class)s
125{
126 protected:
127 public:
128 // Constructor
129 %(class_name)s(ExtMachInst machInst,
130 IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1);
130 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1);
131 %(BasicExecDeclare)s
132};
133}};
134
131 %(BasicExecDeclare)s
132};
133}};
134
135def template SatOpConstructor {{
135def template RegImmRegOpConstructor {{
136 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
137 IntRegIndex _dest,
136 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
137 IntRegIndex _dest,
138 uint32_t _satImm,
138 uint32_t _imm,
139 IntRegIndex _op1)
140 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
139 IntRegIndex _op1)
140 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
141 _dest, _satImm, _op1)
141 _dest, _imm, _op1)
142 {
143 %(constructor)s;
144 }
145}};
146
142 {
143 %(constructor)s;
144 }
145}};
146
147def template SatShiftOpDeclare {{
147def template RegImmRegShiftOpDeclare {{
148class %(class_name)s : public %(base_class)s
149{
150 protected:
151 public:
152 // Constructor
153 %(class_name)s(ExtMachInst machInst,
148class %(class_name)s : public %(base_class)s
149{
150 protected:
151 public:
152 // Constructor
153 %(class_name)s(ExtMachInst machInst,
154 IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
154 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
155 int32_t _shiftAmt, ArmShiftType _shiftType);
156 %(BasicExecDeclare)s
157};
158}};
159
155 int32_t _shiftAmt, ArmShiftType _shiftType);
156 %(BasicExecDeclare)s
157};
158}};
159
160def template SatShiftOpConstructor {{
160def template RegImmRegShiftOpConstructor {{
161 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
162 IntRegIndex _dest,
161 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
162 IntRegIndex _dest,
163 uint32_t _satImm,
163 uint32_t _imm,
164 IntRegIndex _op1,
165 int32_t _shiftAmt,
166 ArmShiftType _shiftType)
167 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
164 IntRegIndex _op1,
165 int32_t _shiftAmt,
166 ArmShiftType _shiftType)
167 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
168 _dest, _satImm, _op1, _shiftAmt, _shiftType)
168 _dest, _imm, _op1, _shiftAmt, _shiftType)
169 {
170 %(constructor)s;
171 }
172}};
169 {
170 %(constructor)s;
171 }
172}};