misc.isa (12236:126ac9da6050) misc.isa (12358:386d26feb00f)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
3// Copyright (c) 2010-2013,2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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609 if (!(condCode == COND_AL || condCode == COND_UC)) {
610 for (int x = 0; x < _numDestRegs; x++) {
611 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
612 }
613 }
614 }
615}};
616
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 597 unchanged lines hidden (view full) ---

609 if (!(condCode == COND_AL || condCode == COND_UC)) {
610 for (int x = 0; x < _numDestRegs; x++) {
611 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
612 }
613 }
614 }
615}};
616
617def template MiscRegRegImmMemOpDeclare {{
618 class %(class_name)s : public %(base_class)s
619 {
620 protected:
621 public:
622 // Constructor
623 %(class_name)s(ExtMachInst machInst,
624 MiscRegIndex _dest, IntRegIndex _op1,
625 uint64_t _imm);
626 Fault execute(ExecContext *, Trace::InstRecord *) const;
627 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
628 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
629 };
630}};
631
632def template Mcr15Execute {{
633 Fault %(class_name)s::execute(ExecContext *xc,
634 Trace::InstRecord *traceData) const
635 {
636 Addr EA;
637 Fault fault = NoFault;
638
639 %(op_decl)s;
640 %(op_rd)s;
641 %(ea_code)s;
642
643 if (%(predicate_test)s) {
644 if (fault == NoFault) {
645 %(memacc_code)s;
646 }
647
648 if (fault == NoFault) {
649 Addr size = 64;
650 EA &= ~(size - 1);
651 fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL);
652 }
653 } else {
654 xc->setPredicate(false);
655 }
656
657 return fault;
658 }
659}};
660
661def template Mcr15InitiateAcc {{
662 Fault %(class_name)s::initiateAcc(ExecContext *xc,
663 Trace::InstRecord *traceData) const
664 {
665 Addr EA;
666 Fault fault = NoFault;
667
668 %(op_decl)s;
669 %(op_rd)s;
670 %(ea_code)s;
671
672 if (%(predicate_test)s) {
673 if (fault == NoFault) {
674 %(memacc_code)s;
675 }
676
677 if (fault == NoFault) {
678 Addr size = 64;
679 EA &= ~(size - 1);
680 fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL);
681 }
682 } else {
683 xc->setPredicate(false);
684 }
685
686 return fault;
687 }
688}};
689
690def template Mcr15CompleteAcc {{
691 Fault %(class_name)s::completeAcc(PacketPtr pkt,
692 ExecContext *xc,
693 Trace::InstRecord *traceData) const
694 {
695 return NoFault;
696 }
697}};