1// -*- mode:c++ -*-
2
| 1// -*- mode:c++ -*-
2
|
3// Copyright (c) 2010 ARM Limited
| 3// Copyright (c) 2010-2013 ARM Limited
|
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template MrsDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43 protected:
44 public:
45 // Constructor
46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
47 %(BasicExecDeclare)s
48};
49}};
50
51def template MrsConstructor {{
52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
53 IntRegIndex _dest)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
55 {
56 %(constructor)s;
57 if (!(condCode == COND_AL || condCode == COND_UC)) {
58 for (int x = 0; x < _numDestRegs; x++) {
59 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
60 }
61 }
62 }
63}};
64
| 4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template MrsDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43 protected:
44 public:
45 // Constructor
46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
47 %(BasicExecDeclare)s
48};
49}};
50
51def template MrsConstructor {{
52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
53 IntRegIndex _dest)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
55 {
56 %(constructor)s;
57 if (!(condCode == COND_AL || condCode == COND_UC)) {
58 for (int x = 0; x < _numDestRegs; x++) {
59 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
60 }
61 }
62 }
63}};
64
|
| 65def template MrsBankedRegDeclare {{
66class %(class_name)s : public %(base_class)s
67{
68 protected:
69 uint8_t byteMask;
70 bool r;
71
72 public:
73 // Constructor
74 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
75 uint8_t _sysM, bool _r);
76 %(BasicExecDeclare)s
77};
78}};
79
80def template MrsBankedRegConstructor {{
81 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
82 IntRegIndex _dest,
83 uint8_t _sysM,
84 bool _r)
85 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest),
86 byteMask(_sysM), r(_r)
87 {
88 %(constructor)s;
89 if (!(condCode == COND_AL || condCode == COND_UC)) {
90 for (int x = 0; x < _numDestRegs; x++) {
91 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
92 }
93 }
94 }
95}};
96
97def template MsrBankedRegDeclare {{
98class %(class_name)s : public %(base_class)s
99{
100 protected:
101 bool r;
102
103 public:
104 // Constructor
105 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
106 uint8_t _sysM, bool _r);
107 %(BasicExecDeclare)s
108};
109}};
110
111def template MsrBankedRegConstructor {{
112 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
113 IntRegIndex _op1,
114 uint8_t _sysM,
115 bool _r)
116 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM),
117 r(_r)
118 {
119 %(constructor)s;
120 if (!(condCode == COND_AL || condCode == COND_UC)) {
121 for (int x = 0; x < _numDestRegs; x++) {
122 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
123 }
124 }
125 }
126}};
127
|
65def template MsrRegDeclare {{
66class %(class_name)s : public %(base_class)s
67{
68 protected:
69 public:
70 // Constructor
71 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
72 %(BasicExecDeclare)s
73};
74}};
75
76def template MsrRegConstructor {{
77 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
78 IntRegIndex _op1,
79 uint8_t mask)
80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
81 {
82 %(constructor)s;
83 if (!(condCode == COND_AL || condCode == COND_UC)) {
84 for (int x = 0; x < _numDestRegs; x++) {
85 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
86 }
87 }
88 }
89}};
90
91def template MsrImmDeclare {{
92class %(class_name)s : public %(base_class)s
93{
94 protected:
95 public:
96 // Constructor
97 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
98 %(BasicExecDeclare)s
99};
100}};
101
102def template MsrImmConstructor {{
103 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
104 uint32_t imm,
105 uint8_t mask)
106 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
107 {
108 %(constructor)s;
109 if (!(condCode == COND_AL || condCode == COND_UC)) {
110 for (int x = 0; x < _numDestRegs; x++) {
111 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
112 }
113 }
114 }
115}};
116
| 128def template MsrRegDeclare {{
129class %(class_name)s : public %(base_class)s
130{
131 protected:
132 public:
133 // Constructor
134 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
135 %(BasicExecDeclare)s
136};
137}};
138
139def template MsrRegConstructor {{
140 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
141 IntRegIndex _op1,
142 uint8_t mask)
143 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
144 {
145 %(constructor)s;
146 if (!(condCode == COND_AL || condCode == COND_UC)) {
147 for (int x = 0; x < _numDestRegs; x++) {
148 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
149 }
150 }
151 }
152}};
153
154def template MsrImmDeclare {{
155class %(class_name)s : public %(base_class)s
156{
157 protected:
158 public:
159 // Constructor
160 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
161 %(BasicExecDeclare)s
162};
163}};
164
165def template MsrImmConstructor {{
166 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
167 uint32_t imm,
168 uint8_t mask)
169 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
170 {
171 %(constructor)s;
172 if (!(condCode == COND_AL || condCode == COND_UC)) {
173 for (int x = 0; x < _numDestRegs; x++) {
174 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
175 }
176 }
177 }
178}};
179
|
| 180def template MrrcOpDeclare {{
181class %(class_name)s : public %(base_class)s
182{
183 protected:
184 public:
185 // Constructor
186 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
187 IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
188 %(BasicExecDeclare)s
189};
190}};
191
192def template MrrcOpConstructor {{
193 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
194 IntRegIndex op1,
195 IntRegIndex dest,
196 IntRegIndex dest2,
197 uint32_t imm)
198 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest,
199 dest2, imm)
200 {
201 %(constructor)s;
202 if (!(condCode == COND_AL || condCode == COND_UC)) {
203 for (int x = 0; x < _numDestRegs; x++) {
204 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
205 }
206 }
207 }
208}};
209
210def template McrrOpDeclare {{
211class %(class_name)s : public %(base_class)s
212{
213 protected:
214 public:
215 // Constructor
216 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
217 IntRegIndex _dest, uint32_t imm);
218 %(BasicExecDeclare)s
219};
220}};
221
222def template McrrOpConstructor {{
223 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
224 IntRegIndex op1,
225 IntRegIndex op2,
226 IntRegIndex dest,
227 uint32_t imm)
228 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2,
229 dest, imm)
230 {
231 %(constructor)s;
232 if (!(condCode == COND_AL || condCode == COND_UC)) {
233 for (int x = 0; x < _numDestRegs; x++) {
234 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
235 }
236 }
237 }
238}};
239
|
117def template ImmOpDeclare {{
118class %(class_name)s : public %(base_class)s
119{
120 protected:
121 public:
122 // Constructor
123 %(class_name)s(ExtMachInst machInst, uint64_t _imm);
124 %(BasicExecDeclare)s
125};
126}};
127
128def template ImmOpConstructor {{
129 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
131 {
132 %(constructor)s;
133 if (!(condCode == COND_AL || condCode == COND_UC)) {
134 for (int x = 0; x < _numDestRegs; x++) {
135 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
136 }
137 }
138 }
139}};
140
141def template RegImmOpDeclare {{
142class %(class_name)s : public %(base_class)s
143{
144 protected:
145 public:
146 // Constructor
147 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
148 %(BasicExecDeclare)s
149};
150}};
151
152def template RegImmOpConstructor {{
153 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
154 IntRegIndex _dest, uint64_t _imm)
155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
156 {
157 %(constructor)s;
158 if (!(condCode == COND_AL || condCode == COND_UC)) {
159 for (int x = 0; x < _numDestRegs; x++) {
160 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
161 }
162 }
163 }
164}};
165
166def template RegRegOpDeclare {{
167class %(class_name)s : public %(base_class)s
168{
169 protected:
170 public:
171 // Constructor
172 %(class_name)s(ExtMachInst machInst,
173 IntRegIndex _dest, IntRegIndex _op1);
174 %(BasicExecDeclare)s
175};
176}};
177
178def template RegRegOpConstructor {{
179 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
180 IntRegIndex _dest, IntRegIndex _op1)
181 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
182 {
183 %(constructor)s;
184 if (!(condCode == COND_AL || condCode == COND_UC)) {
185 for (int x = 0; x < _numDestRegs; x++) {
186 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
187 }
188 }
189 }
190}};
191
192def template RegRegRegImmOpDeclare {{
193class %(class_name)s : public %(base_class)s
194{
195 protected:
196 public:
197 // Constructor
198 %(class_name)s(ExtMachInst machInst,
199 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
200 uint64_t _imm);
201 %(BasicExecDeclare)s
202};
203}};
204
205def template RegRegRegImmOpConstructor {{
206 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
207 IntRegIndex _dest,
208 IntRegIndex _op1,
209 IntRegIndex _op2,
210 uint64_t _imm)
211 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
212 _dest, _op1, _op2, _imm)
213 {
214 %(constructor)s;
215 if (!(condCode == COND_AL || condCode == COND_UC)) {
216 for (int x = 0; x < _numDestRegs; x++) {
217 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
218 }
219 }
220 }
221}};
222
223def template RegRegRegRegOpDeclare {{
224class %(class_name)s : public %(base_class)s
225{
226 protected:
227 public:
228 // Constructor
229 %(class_name)s(ExtMachInst machInst,
230 IntRegIndex _dest, IntRegIndex _op1,
231 IntRegIndex _op2, IntRegIndex _op3);
232 %(BasicExecDeclare)s
233};
234}};
235
236def template RegRegRegRegOpConstructor {{
237 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
238 IntRegIndex _dest,
239 IntRegIndex _op1,
240 IntRegIndex _op2,
241 IntRegIndex _op3)
242 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
243 _dest, _op1, _op2, _op3)
244 {
245 %(constructor)s;
246 if (!(condCode == COND_AL || condCode == COND_UC)) {
247 for (int x = 0; x < _numDestRegs; x++) {
248 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
249 }
250 }
251 }
252}};
253
254def template RegRegRegOpDeclare {{
255class %(class_name)s : public %(base_class)s
256{
257 protected:
258 public:
259 // Constructor
260 %(class_name)s(ExtMachInst machInst,
261 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
262 %(BasicExecDeclare)s
263};
264}};
265
266def template RegRegRegOpConstructor {{
267 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
268 IntRegIndex _dest,
269 IntRegIndex _op1,
270 IntRegIndex _op2)
271 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
272 _dest, _op1, _op2)
273 {
274 %(constructor)s;
275 if (!(condCode == COND_AL || condCode == COND_UC)) {
276 for (int x = 0; x < _numDestRegs; x++) {
277 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
278 }
279 }
280 }
281}};
282
283def template RegRegImmOpDeclare {{
284class %(class_name)s : public %(base_class)s
285{
286 protected:
287 public:
288 // Constructor
289 %(class_name)s(ExtMachInst machInst,
290 IntRegIndex _dest, IntRegIndex _op1,
291 uint64_t _imm);
292 %(BasicExecDeclare)s
293};
294}};
295
296def template RegRegImmOpConstructor {{
297 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
298 IntRegIndex _dest,
299 IntRegIndex _op1,
300 uint64_t _imm)
301 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
302 _dest, _op1, _imm)
303 {
304 %(constructor)s;
305 if (!(condCode == COND_AL || condCode == COND_UC)) {
306 for (int x = 0; x < _numDestRegs; x++) {
307 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
308 }
309 }
310 }
311}};
312
| 240def template ImmOpDeclare {{
241class %(class_name)s : public %(base_class)s
242{
243 protected:
244 public:
245 // Constructor
246 %(class_name)s(ExtMachInst machInst, uint64_t _imm);
247 %(BasicExecDeclare)s
248};
249}};
250
251def template ImmOpConstructor {{
252 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
253 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
254 {
255 %(constructor)s;
256 if (!(condCode == COND_AL || condCode == COND_UC)) {
257 for (int x = 0; x < _numDestRegs; x++) {
258 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
259 }
260 }
261 }
262}};
263
264def template RegImmOpDeclare {{
265class %(class_name)s : public %(base_class)s
266{
267 protected:
268 public:
269 // Constructor
270 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
271 %(BasicExecDeclare)s
272};
273}};
274
275def template RegImmOpConstructor {{
276 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
277 IntRegIndex _dest, uint64_t _imm)
278 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
279 {
280 %(constructor)s;
281 if (!(condCode == COND_AL || condCode == COND_UC)) {
282 for (int x = 0; x < _numDestRegs; x++) {
283 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
284 }
285 }
286 }
287}};
288
289def template RegRegOpDeclare {{
290class %(class_name)s : public %(base_class)s
291{
292 protected:
293 public:
294 // Constructor
295 %(class_name)s(ExtMachInst machInst,
296 IntRegIndex _dest, IntRegIndex _op1);
297 %(BasicExecDeclare)s
298};
299}};
300
301def template RegRegOpConstructor {{
302 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
303 IntRegIndex _dest, IntRegIndex _op1)
304 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
305 {
306 %(constructor)s;
307 if (!(condCode == COND_AL || condCode == COND_UC)) {
308 for (int x = 0; x < _numDestRegs; x++) {
309 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
310 }
311 }
312 }
313}};
314
315def template RegRegRegImmOpDeclare {{
316class %(class_name)s : public %(base_class)s
317{
318 protected:
319 public:
320 // Constructor
321 %(class_name)s(ExtMachInst machInst,
322 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
323 uint64_t _imm);
324 %(BasicExecDeclare)s
325};
326}};
327
328def template RegRegRegImmOpConstructor {{
329 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
330 IntRegIndex _dest,
331 IntRegIndex _op1,
332 IntRegIndex _op2,
333 uint64_t _imm)
334 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
335 _dest, _op1, _op2, _imm)
336 {
337 %(constructor)s;
338 if (!(condCode == COND_AL || condCode == COND_UC)) {
339 for (int x = 0; x < _numDestRegs; x++) {
340 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
341 }
342 }
343 }
344}};
345
346def template RegRegRegRegOpDeclare {{
347class %(class_name)s : public %(base_class)s
348{
349 protected:
350 public:
351 // Constructor
352 %(class_name)s(ExtMachInst machInst,
353 IntRegIndex _dest, IntRegIndex _op1,
354 IntRegIndex _op2, IntRegIndex _op3);
355 %(BasicExecDeclare)s
356};
357}};
358
359def template RegRegRegRegOpConstructor {{
360 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
361 IntRegIndex _dest,
362 IntRegIndex _op1,
363 IntRegIndex _op2,
364 IntRegIndex _op3)
365 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
366 _dest, _op1, _op2, _op3)
367 {
368 %(constructor)s;
369 if (!(condCode == COND_AL || condCode == COND_UC)) {
370 for (int x = 0; x < _numDestRegs; x++) {
371 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
372 }
373 }
374 }
375}};
376
377def template RegRegRegOpDeclare {{
378class %(class_name)s : public %(base_class)s
379{
380 protected:
381 public:
382 // Constructor
383 %(class_name)s(ExtMachInst machInst,
384 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
385 %(BasicExecDeclare)s
386};
387}};
388
389def template RegRegRegOpConstructor {{
390 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
391 IntRegIndex _dest,
392 IntRegIndex _op1,
393 IntRegIndex _op2)
394 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
395 _dest, _op1, _op2)
396 {
397 %(constructor)s;
398 if (!(condCode == COND_AL || condCode == COND_UC)) {
399 for (int x = 0; x < _numDestRegs; x++) {
400 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
401 }
402 }
403 }
404}};
405
406def template RegRegImmOpDeclare {{
407class %(class_name)s : public %(base_class)s
408{
409 protected:
410 public:
411 // Constructor
412 %(class_name)s(ExtMachInst machInst,
413 IntRegIndex _dest, IntRegIndex _op1,
414 uint64_t _imm);
415 %(BasicExecDeclare)s
416};
417}};
418
419def template RegRegImmOpConstructor {{
420 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
421 IntRegIndex _dest,
422 IntRegIndex _op1,
423 uint64_t _imm)
424 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
425 _dest, _op1, _imm)
426 {
427 %(constructor)s;
428 if (!(condCode == COND_AL || condCode == COND_UC)) {
429 for (int x = 0; x < _numDestRegs; x++) {
430 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
431 }
432 }
433 }
434}};
435
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| 436def template RegImmImmOpDeclare {{
437class %(class_name)s : public %(base_class)s
438{
439 protected:
440 public:
441 // Constructor
442 %(class_name)s(ExtMachInst machInst,
443 IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2);
444 %(BasicExecDeclare)s
445};
446}};
447
448def template RegImmImmOpConstructor {{
449 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
450 IntRegIndex _dest,
451 uint64_t _imm1,
452 uint64_t _imm2)
453 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
454 _dest, _imm1, _imm2)
455 {
456 %(constructor)s;
457 if (!(condCode == COND_AL || condCode == COND_UC)) {
458 for (int x = 0; x < _numDestRegs; x++) {
459 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
460 }
461 }
462 }
463}};
464
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313def template RegRegImmImmOpDeclare {{
314class %(class_name)s : public %(base_class)s
315{
316 protected:
317 public:
318 // Constructor
319 %(class_name)s(ExtMachInst machInst,
320 IntRegIndex _dest, IntRegIndex _op1,
321 uint64_t _imm1, uint64_t _imm2);
322 %(BasicExecDeclare)s
323};
324}};
325
326def template RegRegImmImmOpConstructor {{
327 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
328 IntRegIndex _dest,
329 IntRegIndex _op1,
330 uint64_t _imm1,
331 uint64_t _imm2)
332 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
333 _dest, _op1, _imm1, _imm2)
334 {
335 %(constructor)s;
336 if (!(condCode == COND_AL || condCode == COND_UC)) {
337 for (int x = 0; x < _numDestRegs; x++) {
338 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
339 }
340 }
341 }
342}};
343
344def template RegImmRegOpDeclare {{
345class %(class_name)s : public %(base_class)s
346{
347 protected:
348 public:
349 // Constructor
350 %(class_name)s(ExtMachInst machInst,
351 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
352 %(BasicExecDeclare)s
353};
354}};
355
356def template RegImmRegOpConstructor {{
357 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
358 IntRegIndex _dest,
359 uint64_t _imm,
360 IntRegIndex _op1)
361 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
362 _dest, _imm, _op1)
363 {
364 %(constructor)s;
365 if (!(condCode == COND_AL || condCode == COND_UC)) {
366 for (int x = 0; x < _numDestRegs; x++) {
367 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
368 }
369 }
370 }
371}};
372
373def template RegImmRegShiftOpDeclare {{
374class %(class_name)s : public %(base_class)s
375{
376 protected:
377 public:
378 // Constructor
379 %(class_name)s(ExtMachInst machInst,
380 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
381 int32_t _shiftAmt, ArmShiftType _shiftType);
382 %(BasicExecDeclare)s
383};
384}};
385
386def template RegImmRegShiftOpConstructor {{
387 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
388 IntRegIndex _dest,
389 uint64_t _imm,
390 IntRegIndex _op1,
391 int32_t _shiftAmt,
392 ArmShiftType _shiftType)
393 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
394 _dest, _imm, _op1, _shiftAmt, _shiftType)
395 {
396 %(constructor)s;
397 if (!(condCode == COND_AL || condCode == COND_UC)) {
398 for (int x = 0; x < _numDestRegs; x++) {
399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
400 }
401 }
402 }
403}};
404
| 465def template RegRegImmImmOpDeclare {{
466class %(class_name)s : public %(base_class)s
467{
468 protected:
469 public:
470 // Constructor
471 %(class_name)s(ExtMachInst machInst,
472 IntRegIndex _dest, IntRegIndex _op1,
473 uint64_t _imm1, uint64_t _imm2);
474 %(BasicExecDeclare)s
475};
476}};
477
478def template RegRegImmImmOpConstructor {{
479 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
480 IntRegIndex _dest,
481 IntRegIndex _op1,
482 uint64_t _imm1,
483 uint64_t _imm2)
484 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
485 _dest, _op1, _imm1, _imm2)
486 {
487 %(constructor)s;
488 if (!(condCode == COND_AL || condCode == COND_UC)) {
489 for (int x = 0; x < _numDestRegs; x++) {
490 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
491 }
492 }
493 }
494}};
495
496def template RegImmRegOpDeclare {{
497class %(class_name)s : public %(base_class)s
498{
499 protected:
500 public:
501 // Constructor
502 %(class_name)s(ExtMachInst machInst,
503 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
504 %(BasicExecDeclare)s
505};
506}};
507
508def template RegImmRegOpConstructor {{
509 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
510 IntRegIndex _dest,
511 uint64_t _imm,
512 IntRegIndex _op1)
513 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
514 _dest, _imm, _op1)
515 {
516 %(constructor)s;
517 if (!(condCode == COND_AL || condCode == COND_UC)) {
518 for (int x = 0; x < _numDestRegs; x++) {
519 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
520 }
521 }
522 }
523}};
524
525def template RegImmRegShiftOpDeclare {{
526class %(class_name)s : public %(base_class)s
527{
528 protected:
529 public:
530 // Constructor
531 %(class_name)s(ExtMachInst machInst,
532 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
533 int32_t _shiftAmt, ArmShiftType _shiftType);
534 %(BasicExecDeclare)s
535};
536}};
537
538def template RegImmRegShiftOpConstructor {{
539 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
540 IntRegIndex _dest,
541 uint64_t _imm,
542 IntRegIndex _op1,
543 int32_t _shiftAmt,
544 ArmShiftType _shiftType)
545 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
546 _dest, _imm, _op1, _shiftAmt, _shiftType)
547 {
548 %(constructor)s;
549 if (!(condCode == COND_AL || condCode == COND_UC)) {
550 for (int x = 0; x < _numDestRegs; x++) {
551 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
552 }
553 }
554 }
555}};
556
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