1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template MrsDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43 protected:
44 public:
45 // Constructor
46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
47 %(BasicExecDeclare)s
48};
49}};
50
51def template MrsConstructor {{
52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
53 IntRegIndex _dest)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
55 {
56 %(constructor)s;
57 }
58}};
59
60def template MsrRegDeclare {{
61class %(class_name)s : public %(base_class)s
62{
63 protected:
64 public:
65 // Constructor
66 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
67 %(BasicExecDeclare)s
68};
69}};
70
71def template MsrRegConstructor {{
72 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
73 IntRegIndex _op1,
74 uint8_t mask)
75 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
76 {
77 %(constructor)s;
78 }
79}};
80
81def template MsrImmDeclare {{
82class %(class_name)s : public %(base_class)s
83{
84 protected:
85 public:
86 // Constructor
87 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
88 %(BasicExecDeclare)s
89};
90}};
91
92def template MsrImmConstructor {{
93 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
94 uint32_t imm,
95 uint8_t mask)
96 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
97 {
98 %(constructor)s;
99 }
100}};
101
102def template RevOpDeclare {{
103class %(class_name)s : public %(base_class)s
104{
105 protected:
106 public:
107 // Constructor
108 %(class_name)s(ExtMachInst machInst,
109 IntRegIndex _dest, IntRegIndex _op1);
110 %(BasicExecDeclare)s
111};
112}};
113
114def template RevOpConstructor {{
115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
116 IntRegIndex _dest, IntRegIndex _op1)
117 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
118 {
119 %(constructor)s;
120 }
121}};
122
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template MrsDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43 protected:
44 public:
45 // Constructor
46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
47 %(BasicExecDeclare)s
48};
49}};
50
51def template MrsConstructor {{
52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
53 IntRegIndex _dest)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
55 {
56 %(constructor)s;
57 }
58}};
59
60def template MsrRegDeclare {{
61class %(class_name)s : public %(base_class)s
62{
63 protected:
64 public:
65 // Constructor
66 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
67 %(BasicExecDeclare)s
68};
69}};
70
71def template MsrRegConstructor {{
72 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
73 IntRegIndex _op1,
74 uint8_t mask)
75 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
76 {
77 %(constructor)s;
78 }
79}};
80
81def template MsrImmDeclare {{
82class %(class_name)s : public %(base_class)s
83{
84 protected:
85 public:
86 // Constructor
87 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
88 %(BasicExecDeclare)s
89};
90}};
91
92def template MsrImmConstructor {{
93 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
94 uint32_t imm,
95 uint8_t mask)
96 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
97 {
98 %(constructor)s;
99 }
100}};
101
102def template RevOpDeclare {{
103class %(class_name)s : public %(base_class)s
104{
105 protected:
106 public:
107 // Constructor
108 %(class_name)s(ExtMachInst machInst,
109 IntRegIndex _dest, IntRegIndex _op1);
110 %(BasicExecDeclare)s
111};
112}};
113
114def template RevOpConstructor {{
115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
116 IntRegIndex _dest, IntRegIndex _op1)
117 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
118 {
119 %(constructor)s;
120 }
121}};
122
|
123def template SatOpDeclare {{
| 123def template RegImmRegOpDeclare {{
|
124class %(class_name)s : public %(base_class)s
125{
126 protected:
127 public:
128 // Constructor
129 %(class_name)s(ExtMachInst machInst,
| 124class %(class_name)s : public %(base_class)s
125{
126 protected:
127 public:
128 // Constructor
129 %(class_name)s(ExtMachInst machInst,
|
130 IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1);
| 130 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1);
|
131 %(BasicExecDeclare)s
132};
133}};
134
| 131 %(BasicExecDeclare)s
132};
133}};
134
|
135def template SatOpConstructor {{
| 135def template RegImmRegOpConstructor {{
|
136 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
137 IntRegIndex _dest,
| 136 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
137 IntRegIndex _dest,
|
138 uint32_t _satImm,
| 138 uint32_t _imm,
|
139 IntRegIndex _op1)
140 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
| 139 IntRegIndex _op1)
140 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
141 _dest, _satImm, _op1)
| 141 _dest, _imm, _op1)
|
142 {
143 %(constructor)s;
144 }
145}};
146
| 142 {
143 %(constructor)s;
144 }
145}};
146
|
147def template SatShiftOpDeclare {{
| 147def template RegImmRegShiftOpDeclare {{
|
148class %(class_name)s : public %(base_class)s
149{
150 protected:
151 public:
152 // Constructor
153 %(class_name)s(ExtMachInst machInst,
| 148class %(class_name)s : public %(base_class)s
149{
150 protected:
151 public:
152 // Constructor
153 %(class_name)s(ExtMachInst machInst,
|
154 IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
| 154 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
|
155 int32_t _shiftAmt, ArmShiftType _shiftType);
156 %(BasicExecDeclare)s
157};
158}};
159
| 155 int32_t _shiftAmt, ArmShiftType _shiftType);
156 %(BasicExecDeclare)s
157};
158}};
159
|
160def template SatShiftOpConstructor {{
| 160def template RegImmRegShiftOpConstructor {{
|
161 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
162 IntRegIndex _dest,
| 161 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
162 IntRegIndex _dest,
|
163 uint32_t _satImm,
| 163 uint32_t _imm,
|
164 IntRegIndex _op1,
165 int32_t _shiftAmt,
166 ArmShiftType _shiftType)
167 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
| 164 IntRegIndex _op1,
165 int32_t _shiftAmt,
166 ArmShiftType _shiftType)
167 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
168 _dest, _satImm, _op1, _shiftAmt, _shiftType)
| 168 _dest, _imm, _op1, _shiftAmt, _shiftType)
|
169 {
170 %(constructor)s;
171 }
172}};
| 169 {
170 %(constructor)s;
171 }
172}};
|