1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template MrsDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43 protected:
44 public:
45 // Constructor
46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
47 %(BasicExecDeclare)s
48};
49}};
50
51def template MrsConstructor {{
52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
53 IntRegIndex _dest)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
55 {
56 %(constructor)s;
57 if (!(condCode == COND_AL || condCode == COND_UC)) {
58 for (int x = 0; x < _numDestRegs; x++) {
59 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
60 }
61 }
62 }
63}};
64
65def template MsrRegDeclare {{
66class %(class_name)s : public %(base_class)s
67{
68 protected:
69 public:
70 // Constructor
71 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
72 %(BasicExecDeclare)s
73};
74}};
75
76def template MsrRegConstructor {{
77 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
78 IntRegIndex _op1,
79 uint8_t mask)
80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
81 {
82 %(constructor)s;
83 if (!(condCode == COND_AL || condCode == COND_UC)) {
84 for (int x = 0; x < _numDestRegs; x++) {
85 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
86 }
87 }
88 }
89}};
90
91def template MsrImmDeclare {{
92class %(class_name)s : public %(base_class)s
93{
94 protected:
95 public:
96 // Constructor
97 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
98 %(BasicExecDeclare)s
99};
100}};
101
102def template MsrImmConstructor {{
103 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
104 uint32_t imm,
105 uint8_t mask)
106 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
107 {
108 %(constructor)s;
109 if (!(condCode == COND_AL || condCode == COND_UC)) {
110 for (int x = 0; x < _numDestRegs; x++) {
111 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
112 }
113 }
114 }
115}};
116
117def template ImmOpDeclare {{
118class %(class_name)s : public %(base_class)s
119{
120 protected:
121 public:
122 // Constructor
123 %(class_name)s(ExtMachInst machInst, uint64_t _imm);
124 %(BasicExecDeclare)s
125};
126}};
127
128def template ImmOpConstructor {{
129 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
131 {
132 %(constructor)s;
133 if (!(condCode == COND_AL || condCode == COND_UC)) {
134 for (int x = 0; x < _numDestRegs; x++) {
135 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
136 }
137 }
138 }
139}};
140
141def template RegImmOpDeclare {{
142class %(class_name)s : public %(base_class)s
143{
144 protected:
145 public:
146 // Constructor
147 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
148 %(BasicExecDeclare)s
149};
150}};
151
152def template RegImmOpConstructor {{
153 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
154 IntRegIndex _dest, uint64_t _imm)
155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
156 {
157 %(constructor)s;
158 if (!(condCode == COND_AL || condCode == COND_UC)) {
159 for (int x = 0; x < _numDestRegs; x++) {
160 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
161 }
162 }
163 }
164}};
165
166def template RegRegOpDeclare {{
167class %(class_name)s : public %(base_class)s
168{
169 protected:
170 public:
171 // Constructor
172 %(class_name)s(ExtMachInst machInst,
173 IntRegIndex _dest, IntRegIndex _op1);
174 %(BasicExecDeclare)s
175};
176}};
177
178def template RegRegOpConstructor {{
179 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
180 IntRegIndex _dest, IntRegIndex _op1)
181 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
182 {
183 %(constructor)s;
184 if (!(condCode == COND_AL || condCode == COND_UC)) {
185 for (int x = 0; x < _numDestRegs; x++) {
186 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
187 }
188 }
189 }
190}};
191
192def template RegRegRegImmOpDeclare {{
193class %(class_name)s : public %(base_class)s
194{
195 protected:
196 public:
197 // Constructor
198 %(class_name)s(ExtMachInst machInst,
199 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
200 uint64_t _imm);
201 %(BasicExecDeclare)s
202};
203}};
204
205def template RegRegRegImmOpConstructor {{
206 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
207 IntRegIndex _dest,
208 IntRegIndex _op1,
209 IntRegIndex _op2,
210 uint64_t _imm)
211 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
212 _dest, _op1, _op2, _imm)
213 {
214 %(constructor)s;
215 if (!(condCode == COND_AL || condCode == COND_UC)) {
216 for (int x = 0; x < _numDestRegs; x++) {
217 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
218 }
219 }
220 }
221}};
222
223def template RegRegRegRegOpDeclare {{
224class %(class_name)s : public %(base_class)s
225{
226 protected:
227 public:
228 // Constructor
229 %(class_name)s(ExtMachInst machInst,
230 IntRegIndex _dest, IntRegIndex _op1,
231 IntRegIndex _op2, IntRegIndex _op3);
232 %(BasicExecDeclare)s
233};
234}};
235
236def template RegRegRegRegOpConstructor {{
237 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
238 IntRegIndex _dest,
239 IntRegIndex _op1,
240 IntRegIndex _op2,
241 IntRegIndex _op3)
242 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
243 _dest, _op1, _op2, _op3)
244 {
245 %(constructor)s;
246 if (!(condCode == COND_AL || condCode == COND_UC)) {
247 for (int x = 0; x < _numDestRegs; x++) {
248 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
249 }
250 }
251 }
252}};
253
254def template RegRegRegOpDeclare {{
255class %(class_name)s : public %(base_class)s
256{
257 protected:
258 public:
259 // Constructor
260 %(class_name)s(ExtMachInst machInst,
261 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
262 %(BasicExecDeclare)s
263};
264}};
265
266def template RegRegRegOpConstructor {{
267 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
268 IntRegIndex _dest,
269 IntRegIndex _op1,
270 IntRegIndex _op2)
271 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
272 _dest, _op1, _op2)
273 {
274 %(constructor)s;
275 if (!(condCode == COND_AL || condCode == COND_UC)) {
276 for (int x = 0; x < _numDestRegs; x++) {
277 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
278 }
279 }
280 }
281}};
282
283def template RegRegImmOpDeclare {{
284class %(class_name)s : public %(base_class)s
285{
286 protected:
287 public:
288 // Constructor
289 %(class_name)s(ExtMachInst machInst,
290 IntRegIndex _dest, IntRegIndex _op1,
291 uint64_t _imm);
292 %(BasicExecDeclare)s
293};
294}};
295
296def template RegRegImmOpConstructor {{
297 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
298 IntRegIndex _dest,
299 IntRegIndex _op1,
300 uint64_t _imm)
301 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
302 _dest, _op1, _imm)
303 {
304 %(constructor)s;
305 if (!(condCode == COND_AL || condCode == COND_UC)) {
306 for (int x = 0; x < _numDestRegs; x++) {
307 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
308 }
309 }
310 }
311}};
312
313def template RegRegImmImmOpDeclare {{
314class %(class_name)s : public %(base_class)s
315{
316 protected:
317 public:
318 // Constructor
319 %(class_name)s(ExtMachInst machInst,
320 IntRegIndex _dest, IntRegIndex _op1,
321 uint64_t _imm1, uint64_t _imm2);
322 %(BasicExecDeclare)s
323};
324}};
325
326def template RegRegImmImmOpConstructor {{
327 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
328 IntRegIndex _dest,
329 IntRegIndex _op1,
330 uint64_t _imm1,
331 uint64_t _imm2)
332 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
333 _dest, _op1, _imm1, _imm2)
334 {
335 %(constructor)s;
336 if (!(condCode == COND_AL || condCode == COND_UC)) {
337 for (int x = 0; x < _numDestRegs; x++) {
338 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
339 }
340 }
341 }
342}};
343
344def template RegImmRegOpDeclare {{
345class %(class_name)s : public %(base_class)s
346{
347 protected:
348 public:
349 // Constructor
350 %(class_name)s(ExtMachInst machInst,
351 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
352 %(BasicExecDeclare)s
353};
354}};
355
356def template RegImmRegOpConstructor {{
357 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
358 IntRegIndex _dest,
359 uint64_t _imm,
360 IntRegIndex _op1)
361 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
362 _dest, _imm, _op1)
363 {
364 %(constructor)s;
365 if (!(condCode == COND_AL || condCode == COND_UC)) {
366 for (int x = 0; x < _numDestRegs; x++) {
367 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
368 }
369 }
370 }
371}};
372
373def template RegImmRegShiftOpDeclare {{
374class %(class_name)s : public %(base_class)s
375{
376 protected:
377 public:
378 // Constructor
379 %(class_name)s(ExtMachInst machInst,
380 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
381 int32_t _shiftAmt, ArmShiftType _shiftType);
382 %(BasicExecDeclare)s
383};
384}};
385
386def template RegImmRegShiftOpConstructor {{
387 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
388 IntRegIndex _dest,
389 uint64_t _imm,
390 IntRegIndex _op1,
391 int32_t _shiftAmt,
392 ArmShiftType _shiftType)
393 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
394 _dest, _imm, _op1, _shiftAmt, _shiftType)
395 {
396 %(constructor)s;
397 if (!(condCode == COND_AL || condCode == COND_UC)) {
398 for (int x = 0; x < _numDestRegs; x++) {
399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
400 }
401 }
402 }
403}};
404
405def template ClrexDeclare {{
406 /**
407 * Static instruction class for "%(mnemonic)s".
408 */
409 class %(class_name)s : public %(base_class)s
410 {
411 public:
412
413 /// Constructor.
414 %(class_name)s(ExtMachInst machInst);
415
416 %(BasicExecDeclare)s
417
418 %(InitiateAccDeclare)s
419
420 %(CompleteAccDeclare)s
421 };
422}};
423
424def template ClrexInitiateAcc {{
425 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
426 Trace::InstRecord *traceData) const
427 {
428 Fault fault = NoFault;
429 %(op_decl)s;
430 %(op_rd)s;
431
432 if (%(predicate_test)s)
433 {
434 if (fault == NoFault) {
435 unsigned memAccessFlags = Request::CLEAR_LL |
436 ArmISA::TLB::AlignWord | Request::LLSC;
437 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
438 }
439 } else {
440 xc->setPredicate(false);
441 if (fault == NoFault && machInst.itstateMask != 0) {
442 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
443 }
444 }
445
446 return fault;
447 }
448}};
449
450def template ClrexCompleteAcc {{
451 Fault %(class_name)s::completeAcc(PacketPtr pkt,
452 %(CPU_exec_context)s *xc,
453 Trace::InstRecord *traceData) const
454 {
455 if (machInst.itstateMask != 0) {
456 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
457 }
458
459 return NoFault;
460 }
461}};
462