1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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49}};
50
51def template MrsConstructor {{
52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
53 IntRegIndex _dest)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
55 {
56 %(constructor)s;
57 if (!(condCode == COND_AL || condCode == COND_UC)) {
58 for (int x = 0; x < _numDestRegs; x++) {
59 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
60 }
61 }
62 }
63}};
64
65def template MsrRegDeclare {{
66class %(class_name)s : public %(base_class)s
67{
68 protected:
69 public:

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75
76def template MsrRegConstructor {{
77 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
78 IntRegIndex _op1,
79 uint8_t mask)
80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
81 {
82 %(constructor)s;
83 if (!(condCode == COND_AL || condCode == COND_UC)) {
84 for (int x = 0; x < _numDestRegs; x++) {
85 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
86 }
87 }
88 }
89}};
90
91def template MsrImmDeclare {{
92class %(class_name)s : public %(base_class)s
93{
94 protected:
95 public:

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101
102def template MsrImmConstructor {{
103 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
104 uint32_t imm,
105 uint8_t mask)
106 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
107 {
108 %(constructor)s;
109 if (!(condCode == COND_AL || condCode == COND_UC)) {
110 for (int x = 0; x < _numDestRegs; x++) {
111 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
112 }
113 }
114 }
115}};
116
117def template ImmOpDeclare {{
118class %(class_name)s : public %(base_class)s
119{
120 protected:
121 public:
122 // Constructor
123 %(class_name)s(ExtMachInst machInst, uint64_t _imm);
124 %(BasicExecDeclare)s
125};
126}};
127
128def template ImmOpConstructor {{
129 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
131 {
132 %(constructor)s;
133 if (!(condCode == COND_AL || condCode == COND_UC)) {
134 for (int x = 0; x < _numDestRegs; x++) {
135 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
136 }
137 }
138 }
139}};
140
141def template RegImmOpDeclare {{
142class %(class_name)s : public %(base_class)s
143{
144 protected:
145 public:

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150}};
151
152def template RegImmOpConstructor {{
153 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
154 IntRegIndex _dest, uint64_t _imm)
155 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
156 {
157 %(constructor)s;
158 if (!(condCode == COND_AL || condCode == COND_UC)) {
159 for (int x = 0; x < _numDestRegs; x++) {
160 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
161 }
162 }
163 }
164}};
165
166def template RegRegOpDeclare {{
167class %(class_name)s : public %(base_class)s
168{
169 protected:
170 public:

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176}};
177
178def template RegRegOpConstructor {{
179 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
180 IntRegIndex _dest, IntRegIndex _op1)
181 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
182 {
183 %(constructor)s;
184 if (!(condCode == COND_AL || condCode == COND_UC)) {
185 for (int x = 0; x < _numDestRegs; x++) {
186 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
187 }
188 }
189 }
190}};
191
192def template RegRegRegImmOpDeclare {{
193class %(class_name)s : public %(base_class)s
194{
195 protected:
196 public:

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207 IntRegIndex _dest,
208 IntRegIndex _op1,
209 IntRegIndex _op2,
210 uint64_t _imm)
211 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
212 _dest, _op1, _op2, _imm)
213 {
214 %(constructor)s;
215 if (!(condCode == COND_AL || condCode == COND_UC)) {
216 for (int x = 0; x < _numDestRegs; x++) {
217 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
218 }
219 }
220 }
221}};
222
223def template RegRegRegRegOpDeclare {{
224class %(class_name)s : public %(base_class)s
225{
226 protected:
227 public:

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238 IntRegIndex _dest,
239 IntRegIndex _op1,
240 IntRegIndex _op2,
241 IntRegIndex _op3)
242 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
243 _dest, _op1, _op2, _op3)
244 {
245 %(constructor)s;
246 if (!(condCode == COND_AL || condCode == COND_UC)) {
247 for (int x = 0; x < _numDestRegs; x++) {
248 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
249 }
250 }
251 }
252}};
253
254def template RegRegRegOpDeclare {{
255class %(class_name)s : public %(base_class)s
256{
257 protected:
258 public:

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267 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
268 IntRegIndex _dest,
269 IntRegIndex _op1,
270 IntRegIndex _op2)
271 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
272 _dest, _op1, _op2)
273 {
274 %(constructor)s;
275 if (!(condCode == COND_AL || condCode == COND_UC)) {
276 for (int x = 0; x < _numDestRegs; x++) {
277 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
278 }
279 }
280 }
281}};
282
283def template RegRegImmOpDeclare {{
284class %(class_name)s : public %(base_class)s
285{
286 protected:
287 public:

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297 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
298 IntRegIndex _dest,
299 IntRegIndex _op1,
300 uint64_t _imm)
301 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
302 _dest, _op1, _imm)
303 {
304 %(constructor)s;
305 if (!(condCode == COND_AL || condCode == COND_UC)) {
306 for (int x = 0; x < _numDestRegs; x++) {
307 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
308 }
309 }
310 }
311}};
312
313def template RegRegImmImmOpDeclare {{
314class %(class_name)s : public %(base_class)s
315{
316 protected:
317 public:

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328 IntRegIndex _dest,
329 IntRegIndex _op1,
330 uint64_t _imm1,
331 uint64_t _imm2)
332 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
333 _dest, _op1, _imm1, _imm2)
334 {
335 %(constructor)s;
336 if (!(condCode == COND_AL || condCode == COND_UC)) {
337 for (int x = 0; x < _numDestRegs; x++) {
338 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
339 }
340 }
341 }
342}};
343
344def template RegImmRegOpDeclare {{
345class %(class_name)s : public %(base_class)s
346{
347 protected:
348 public:

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357 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
358 IntRegIndex _dest,
359 uint64_t _imm,
360 IntRegIndex _op1)
361 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
362 _dest, _imm, _op1)
363 {
364 %(constructor)s;
365 if (!(condCode == COND_AL || condCode == COND_UC)) {
366 for (int x = 0; x < _numDestRegs; x++) {
367 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
368 }
369 }
370 }
371}};
372
373def template RegImmRegShiftOpDeclare {{
374class %(class_name)s : public %(base_class)s
375{
376 protected:
377 public:

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389 uint64_t _imm,
390 IntRegIndex _op1,
391 int32_t _shiftAmt,
392 ArmShiftType _shiftType)
393 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
394 _dest, _imm, _op1, _shiftAmt, _shiftType)
395 {
396 %(constructor)s;
397 if (!(condCode == COND_AL || condCode == COND_UC)) {
398 for (int x = 0; x < _numDestRegs; x++) {
399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
400 }
401 }
402 }
403}};
404
405def template ClrexDeclare {{
406 /**
407 * Static instruction class for "%(mnemonic)s".
408 */
409 class %(class_name)s : public %(base_class)s

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