mem64.isa (14150:1391e94a7b95) mem64.isa (14157:0f836da31d9c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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846
847def template AmoOpConstructor {{
848 %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 _dest, _base, _result)
852 {
853 %(constructor)s;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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846
847def template AmoOpConstructor {{
848 %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 _dest, _base, _result)
852 {
853 %(constructor)s;
854
854 flags[IsStore] = false;
855 flags[IsLoad] = false;
855 }
856}};
857
858def template AmoPairOpDeclare {{
859 class %(class_name)s : public %(base_class)s
860 {
861 public:
862 uint32_t d2_src ;

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892 uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
893
894 d2_src = _numSrcRegs ;
895 _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
896 r2_src = _numSrcRegs ;
897 _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
898 r2_dst = _numDestRegs ;
899 _destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
856 }
857}};
858
859def template AmoPairOpDeclare {{
860 class %(class_name)s : public %(base_class)s
861 {
862 public:
863 uint32_t d2_src ;

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893 uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
894
895 d2_src = _numSrcRegs ;
896 _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
897 r2_src = _numSrcRegs ;
898 _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
899 r2_dst = _numDestRegs ;
900 _destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
900
901 flags[IsStore] = false;
902 flags[IsLoad] = false;
901 }
902}};
903
904def template AmoArithmeticOpDeclare {{
905 class %(class_name)s : public %(base_class)s
906 {
907 public:
908 bool isXZR ;

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927 %(class_name)s::%(class_name)s(ExtMachInst machInst,
928 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
929 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
930 _dest, _base, _result)
931 {
932 %(constructor)s;
933 isXZR = false;
934 uint32_t r2 = RegId(IntRegClass, dest).index() ;
903 }
904}};
905
906def template AmoArithmeticOpDeclare {{
907 class %(class_name)s : public %(base_class)s
908 {
909 public:
910 bool isXZR ;

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929 %(class_name)s::%(class_name)s(ExtMachInst machInst,
930 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
931 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
932 _dest, _base, _result)
933 {
934 %(constructor)s;
935 isXZR = false;
936 uint32_t r2 = RegId(IntRegClass, dest).index() ;
937 flags[IsStore] = false;
938 flags[IsLoad] = false;
935 if (r2 == 31){
939 if (r2 == 31){
936 flags[IsReadBarrier] = false;
937 isXZR = true;
938 }
939 }
940}};
940 isXZR = true;
941 }
942 }
943}};